HD64F7144F50V Datasheet, PDF (379/932 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

11. Multi-Function Timer Pulse Unit (MTU)
11.7.16 Contention between Overflow/Underflow and Counter Clearing
If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is
not set and TCNT clearing takes precedence.
Figure 11.83 shows the operation timing when a TGR compare match is specified as the clearing
source, and when H'FFFF is set in TGR.
Pφ
TCNT input
clock
TCNT
Counter clear
signal
TGF
TCFV
H'FFFF
Disabled
H'0000
Figure 11.83 Contention between Overflow and Counter Clearing
Rev.4.00 Mar. 27, 2008 Page 333 of 882
REJ09B0108-0400