HD64F7144F50V Datasheet, PDF (105/932 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

4. Clock Pulse Generator
A circuitry shown in figure 4.6 is recommended as an external circuitry around the PLL. Place
oscillation stabilization capacitor C1 close to the PLLCAP pin, and ensure that no other signal
lines cross this line. Separate the PLL power lines (PLLVcc, PLLVss) and the system power lines
(Vcc, Vss) at the board power supply source, and be sure to insert bypass capacitors CB and CPB
close to the pins.
PLLCAP
PLLV_CC
PLLV_SS
R1=3kΩ C1: 470 pF
Rp=200Ω
CPB = 0.1 μF^*
V_CC
CB = 0.1 μF^*
V_SS
(Values are recommended values.)
Note: * CB and CPB are laminated ceramic type.
Figure 4.6 Recommended External Circuitry around PLL
In principle, electromagnetic waves are emitted from an LSI in operation. This LSI regards the
lower of the system clock (φ) and the peripheral clock (Pφ) as fundamental (for example, if φ = 40
MHz and Pφ = 40 MHz, then 40 MHz), and the peak of electromagnetic waves is in the high
frequency band. When this LSI is used adjacent to apparatuses sensible to electromagnetic waves
such as FM/VHF band receivers, it is recommended to use a board with at least four layers and
provide a layer exclusive to the system ground.
Rev.4.00 Mar. 27, 2008 Page 59 of 882
REJ09B0108-0400