HD64F7144F50V Datasheet, PDF (124/932 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

6. Interrupt Controller (INTC)
Figure 6.1 shows a block diagram of the INTC.
IRQOUT
NMI
IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
UBC
DMAC
H-UDI
DTC
MTU
CMT
A/D
SCI
WDT
IIC
I/O
Input
control
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
ICR1
ICR2
ISR
Com-
parator
IPR
IPRA to IPRJ
Interrupt
request
SR
I3 I2 I1 I0
CPU
DTER
DTC
Module bus
Bus
interface
INTC
[Legend]
UBC: User break controller
DMAC: Direct memory access controller
H-UDI: User debug interface
DTC: Data transfer controller
MTU: Multifunction timer unit
CMT: Compare match timer
A/D: A/D converter
SCI:
Serial communication interface
WDT:
Watchdog timer
IIC:
IIC bus interface
I/O:
I/O port (port output control unit)
ICR1, ICR2: Interrupt control register
ISR:
IRQ status register
IPRA to IPRJ: Interrupt priority registers A to J
SR:
Status register
Figure 6.1 INTC Block Diagram
Rev.4.00 Mar. 27, 2008 Page 78 of 882
REJ09B0108-0400