HD64F7144F50V Datasheet, PDF (198/932 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

9. Bus State Controller (BSC)
9.5.3 Wait Control Register 1 (WCR1)
WCR1 is a 16-bit readable/writable register that specifies the number of wait cycles (0 to 15) for
each CS space.
Bit Bit Name Initial Value R/W Description
15 W33
1
14 W32
1
13 W31
1
12 W30
1
R/W CS3 and CS7 Space Wait Specification
R/W _{These bits specify the number of waits for CS3 and}
R/W _{CS7 space access.}
R/W
0000: No wait (external wait input disabled)
0001: One wait (external wait input enabled)
...
1111: 15 waits (external wait input enabled)
11 W23
1
10 W22
1
9 W21
1
8 W20
1
R/W CS2 and CS6 Space Wait Specification
R/W _{These bits specify the number of waits for CS2 and}
R/W _{CS6 space access.}
R/W
0000: No wait (external wait input disabled)
0001: One wait (external wait input enabled)
...
1111: 15 waits (external wait input enabled)
7 W13
1
6 W12
1
5 W11
1
4 W10
1
R/W CS1 and CS5 Space Wait Specification
R/W _{These bits specify the number of waits for CS1 and}
R/W _{CS5 space access.}
R/W
0000: No wait (external wait input disabled)
0001: One wait (external wait input enabled)
...
1111: 15 waits (external wait input enabled)
3 W03
1
2 W02
1
1 W01
1
0 W00
1
R/W CS0 and CS4 Space Wait Specification
R/W _{These bits specify the number of waits for CS0 and}
R/W _{CS4 space access.}
R/W
0000: No wait (external wait input disabled)
0001: One wait (external wait input enabled)
...
1111: 15 waits (external wait input enabled)
Rev.4.00 Mar. 27, 2008 Page 152 of 882
REJ09B0108-0400