HD64F7144F50V Datasheet, PDF (205/932 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

9. Bus State Controller (BSC)
CK
Address
T1
T2
Tidle
T1
T2
CSn
CSm
RD
WRxx
Data
CSn space read
Idle cycles
CSm space write
Figure 9.7 Example of Idle Cycle Insertion
Bits IW31 and IW30 in BCR2 specify the number of idle cycles inserted in the case of a write
cycle to CS3 and CS7 spaces or a read access to different space after CS3 and CS7 space read.
Bits IW21 and IW20 specify the number of idle cycles inserted for CS2 and CS6 spaces, bits
IW11 and IW10 specify for CS1 and CS5 spaces, and bits IW01 and IW00 specify for CS0 and
CS4 spaces, respectively.
Rev.4.00 Mar. 27, 2008 Page 159 of 882
REJ09B0108-0400