HD64F7144F50V Datasheet, PDF (48/932 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

1. Overview
1.1 Features
• Central processing unit with an internal 32-bit RISC (Reduced Instruction Set Computer)
architecture
⎯ Instruction length: 16-bit fixed length for improved code efficiency
⎯ Load-store architecture (basic operations are executed between registers)
⎯ Sixteen 32-bit general registers
⎯ Five-stage pipeline
⎯ On-chip multiplier: multiplication operations (32 bits × 32 bits → 64 bits) executed in two
to four cycles
⎯ C language-oriented 62 basic instructions
• Various peripheral functions
⎯ Direct memory access controller (DMAC)
⎯ Data transfer controller (DTC)
⎯ Multifunction timer/pulse unit (MTU)
⎯ Compare match timer (CMT)
⎯ Watchdog timer (WDT)
⎯ Asynchronous or clocked synchronous serial communication interface (SCI)
⎯ I²C bus interface (IIC)*¹
⎯ 10-bit A/D converter
⎯ Clock pulse generator
⎯ User break controller (UBC)
⎯ User debugging interface (H-UDI)*²
⎯ Advanced user debugger (AUD)*²
Notes: 1. Option
2. Supported only for flash memory version.
Rev.4.00 Mar. 27, 2008 Page 2 of 882
REJ09B0108-0400