HD64F7144F50V Datasheet, PDF (597/932 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

A/D conversion time (t_CONV)
A/D conversion start Analog input
delay time (tD) sampling time (tSPL)
ADCSR
write
cycle
Pφ
15. A/D Converter
Address
Internal write
signal
ADST write timing
Analog input
sampling time
A/D converter
Idle state
Sample-and-hold A/D conversion
ADF
End of A/D conversion
Figure 15.2 A/D Conversion Timing
Table 15.3 A/D Conversion Time (Single Mode)
CKS1 = 0
CKS0 = 0
CKS0 = 1
Item
Symbol Min Typ Max Min Typ Max
A/D conversion t_D
start delay
31 — 62 15 — 30
Input sampling t_SPL
time
— 256 — — 128 —
A/D conversion t_CONV
time
1024 — 1055 515 — 530
Note: All values represent the number of states for Pφ.
CKS1 = 1
CKS0 = 0
CKS0 = 1
Min Typ Max Min Typ Max
7 — 14 3 — 6
— 64 — — 32 —
259 — 266 131 — 134
Rev.4.00 Mar. 27, 2008 Page 551 of 882
REJ09B0108-0400