HD64F7144F50V Datasheet, PDF (776/932 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

24. Power-Down Modes
Oscillator
CK
NMI input
NMIE bit
SSBY bit
LSI state ^Program
NMI
exception
Exception
execution state _handling service routine
Software
standby mode
Oscillation WDT NMI exception
start time setting time handling
Oscillation stabilization
time
Figure 24.1 NMI Timing in Software Standby Mode (Application Example)
24.3.3 Module Standby Mode
Module standby mode can be set for individual on-chip peripheral functions.
When the corresponding MSTP bit in MSTCR is set to 1, module operation stops at the end of the
bus cycle and a transition is made to module standby mode. The CPU continues operating
independently.
When the corresponding MSTP bit is cleared to 0, module standby mode is cleared and the
module starts operating at the end of the bus cycle. In some of the modules that have entered
module standby mode, register values are initialized. Therefore, set registers again when operating
the modules.
After reset clearing, the I²C, SCI, MTU, CMT, and A/D converter are in module standby mode.
The modules of registers in module standby mode cannot be read or written to.
Rev.4.00 Mar. 27, 2008 Page 730 of 882
REJ09B0108-0400