HD64F7144F50V Datasheet, PDF (579/932 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

14. I²C Bus Interface (IIC) Option
SDA
SCL
Internal clock
BBSY bit
Bit 0
A
8
9
Stop condition
(a)
Master-reception mode
ICDR read-disabled
period
Start condition
Execution of the instruction _{Confirmation of stop-condition}
that sets the stop condition _{(reading 0 from BBSY)}
(writing 0 to BBSY and SCP)
Start condition set
Figure 14.29 Points for Caution in Reading Data Received by Master Reception
8. Points for Caution in Setting the Start Condition for Re-transmission
Figure 14.30 shows the timing and flowchart of the setting of the start condition for re-
transmission, and the timing with which the data is continuously written to ICDR. Write the
transmit data to ICDR after the start condition for re-transmission is issued and then the start
condition is actually generated.
Rev.4.00 Mar. 27, 2008 Page 533 of 882
REJ09B0108-0400