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HD64F7144F50V Datasheet, PDF (453/932 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents | |||
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13. Serial Communication Interface (SCI)
13.3.7 Serial Status Register (SSR)
SSR is a register containing status flags of the SCI and multiprocessor bits for transfer. 1 cannot
be written to flags TDRE, RDRF, ORER, PER, and FER; they can only be cleared.
Some bit functions of SSR differ between normal serial communication interface mode and smart
card interface mode.
⢠Normal serial communication interface mode (when SMIF in SDCR is 0)
Bit Bit Name Initial Value R/W Description
7 TDRE
1
R/(W)* Transmit Data Register Empty
Indicates whether TDR contains transmit data.
[Setting conditions]
⢠Power-on reset or software standby mode
⢠When the TE bit in SCR is 0
⢠When data is transferred from TDR to TSR and
data can be written to TDR
[Clearing conditions]
⢠When 0 is written to TDRE after reading TDRE =
1
⢠When the DMAC is activated by a TXI interrupt
request.
⢠When the DTC is activated by a TXI interrupt
request and transferred data to TDR while the
DISEL bit in DTMR of DTC is 0.
Rev.4.00 Mar. 27, 2008 Page 407 of 882
REJ09B0108-0400
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