HD64F7144F50V Datasheet, PDF (302/932 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

11. Multi-Function Timer Pulse Unit (MTU)
Bit Bit Name Initial value R/W Description
3 FB
0
R/W External Feedback Signal Enable
This bit selects whether the switching of the output of
the positive/reverse phase is carried out
automatically with the MTU/channel 0 TGRA, TGRB,
TGRC input capture signals or by writing 0 or 1 to bits
2 to 0 in TGCR.
0: Output switching is external input (Input sources
are channel 0 TGRA, TGRB, TGRC input capture
signal)
1: Output switching is carried out by software
(TGCR's UF, VF, WF settings).
2 WF
0
R/W Output Phase Switch 2 to 0
1 VF
0
0 UF
0
R/W These bits set the positive phase/negative phase
R/W ^{output phase on or off state. The setting of these bits}
is valid only when the FB bit in this register is set to 1.
In this case, the setting of bits 2 to 0 is a substitute
for external input. See table 11.28.
Table 11.28 Output level Select Function
Bit 2
WF
0
Bit 1
VF
0
1
1
0
1
Bit 0
UF
0
1
0
1
0
1
0
1
TIOC3B
U Phase
OFF
ON
OFF
OFF
OFF
ON
OFF
OFF
TIOC4A
V Phase
OFF
OFF
ON
ON
OFF
OFF
OFF
OFF
Function
TIOC4B TIOC3D
W Phase U Phase
OFF
OFF
OFF
OFF
OFF
ON
OFF
OFF
ON
OFF
OFF
OFF
ON
ON
OFF
OFF
TIOC4C
V Phase
OFF
OFF
OFF
OFF
ON
ON
OFF
OFF
TIOC4D
W Phase
OFF
ON
OFF
ON
OFF
OFF
OFF
OFF
Rev.4.00 Mar. 27, 2008 Page 256 of 882
REJ09B0108-0400