HD64F7144F50V Datasheet, PDF (200/932 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

9. Bus State Controller (BSC)
9.6 Accessing External Space
A strobe signal is output in external space accesses to provide primarily for SRAM or ROM direct
connections.
9.6.1 Basic Timing
External access bus cycles are performed in 2 states. Figure 9.3 shows the basic timing of external
space access.
CK
Address
CSn
Read
RD
Data
Write
WRxx
Data
DACK
T1
T2
Figure 9.3 Basic Timing of External Space Access
During a read, irrespective of operand size, all bits in the data bus width for the access space
(address) accessed by RD signal are fetched by the LSI.
During a write, the WRHH (bits 31 to 24), the WRHL (bits 23 to 16), the WRH (bits 15 to 8), and
the WRL (bits 7 to 0) signal indicate the byte location to be written.
Rev.4.00 Mar. 27, 2008 Page 154 of 882
REJ09B0108-0400