HD64F7144F50V Datasheet, PDF (541/932 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

14. I²C Bus Interface (IIC) Option
14.4.2 Initialization
Initialize the IIC following the procedure shown below before starting the data transmission or
reception.
Initialization start
Set MSTP21 = 0 (MSTCR1) Cancel module stop mode
Set IICE = 1 (SCRX)
Set ICE = 0 (ICCR)
Set SAR, SARX
Set ICE = 1 (ICCR)
Enable the CPU access to the IIC control registerand data
register.
Enable SAR and SARX to be accessed
Set the first slave address, second slave address,and IIC
transfer format
(SVA6 to SVA0, FS, SVAX6 to SVAX0, FSX)
Enable ICMR and ICDR to be accessed
Set PBCR1, PBCR2
Set ICSR
Set SCRX
Set ICMR
Set SCRX
Set ICCR
Use SCL/SDA pin as an I²C port
Set acknowledge bit
(ACKB)
Set transfer rate
(IICX)
Set transfer format, wait insertion, and transfer rate
(MLS, WAIT, and CKS2 to CKS0)
Enable interrupt
(STOPIM and HNDS)
Set interrupt enable, transfer mode, and acknowledge decision
(IEIC, MST, TRS, and ACKE)
Read the IRIC flag in ICCR
No
Clear the IRIC flag in ICCR
IRIC = 0?
Yes
<<Transmission/reception start>>
Figure 14.6 An Example of IIC Initialization Flowchart
Rev.4.00 Mar. 27, 2008 Page 495 of 882
REJ09B0108-0400