HD64F7144F50V Datasheet, PDF (250/932 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

10. Direct Memory Access Controller (DMAC)
The reload function can be executed whether the transfer data size is 8, 16, or 32 bits.
DMATCR_2, which specifies the number of transfers, is decremented by 1 at the end of every
single-transfer-unit transfer, regardless of whether the reload function is on or off. Therefore,
when using the reload function in the on state, a multiple of 4 must be specified in DMATCR_2.
Operation will not be guaranteed if any other value is set. Also, the counter which counts the
occurrence of four transfers for address reloading is reset by clearing of the DME bit in DMAOR
or the DE bit in CHCR_2, setting of the transfer end flag (the TE bit in CHCR_2), NMI input, and
setting of the AE flag (address error generation in DMAC transfer), as well as by a reset and in
software standby mode, but SAR_2, DAR_2, DMATCR_2, and other registers are not reset.
Consequently, when one of these sources occurs, there is a mixture of initialized counters and
uninitialized registers in the DMAC, and incorrect operation may result if a restart is executed in
this state. Therefore, when one of the above sources, other than TE setting, occurs during use of
the address reload function, SAR_2, DAR_2, and DMATCR_2 settings must be carried out before
re-execution.
10.4.7 DMA Transfer Ending Conditions
The DMA transfer ending conditions vary for individual channels ending and for all channels
ending together.
Individual Channel Ending Conditions: There are two ending conditions. A transfer ends when
the value of the channel’s DMA transfer count register (DMATCR) is 0, or when the DE bit of the
channel’s CHCR is cleared to 0.
• When DMATCR is 0: When the DMATCR value becomes 0 and the corresponding channel's
DMA transfer ends, the transfer end flag bit (TE) is set in the CHCR. If the IE (interrupt
enable) bit has been set, a DMAC interrupt (DEI) is requested of the CPU.
• When DE of CHCR is 0: Software can halt a DMA transfer by clearing the DE bit in the
channel’s CHCR. The TE bit is not set when this happens.
Rev.4.00 Mar. 27, 2008 Page 204 of 882
REJ09B0108-0400