HD64F7144F50V Datasheet, PDF (572/932 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

14. I²C Bus Interface (IIC) Option
14.4.9 Noise Canceller
The states on the SCL and SDA pins are fetched internally via the noise canceller. Figure 14.28 is
a block diagram of the noise canceller.
The noise canceller consists of a 2-stage latch circuit and match-detection circuit, which are
connected in series. The input signal on the SCL pin (or on the SDA pin) is sampled on the system
clock; when the two latch outputs match, the given level is then sent to the next stage. If the two
values do not match, the existing value is maintained.
Sampling clock
SCL input signal or
SDA input signal
C
D
Q
Latch
C
D
Q
Latch
Match-detection
circuit
Internal SCL signal or
Internal SDA signal
System clock period
Sampling clock
Figure 14.28 Block Diagram of the Noise Canceller
14.4.10 Initialization of Internal State
This IIC module has a function for forcible initialization of its internal state if a deadlock occurs
during communication.
Initialization is executed by clearing ICE bit.
Rev.4.00 Mar. 27, 2008 Page 526 of 882
REJ09B0108-0400