HD64F7144F50V Datasheet, PDF (84/932 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

2. CPU
• Arithmetic Operation Instructions
Instruction
Instruction Code
ADD
Rm,Rn 0011nnnnmmmm1100
ADD
#imm,Rn 0111nnnniiiiiiii
ADDC Rm,Rn 0011nnnnmmmm1110
ADDV Rm,Rn 0011nnnnmmmm1111
CMP/EQ #imm,R0 10001000iiiiiiii
CMP/EQ Rm,Rn 0011nnnnmmmm0000
CMP/HS Rm,Rn 0011nnnnmmmm0010
CMP/GE Rm,Rn 0011nnnnmmmm0011
CMP/HI Rm,Rn 0011nnnnmmmm0110
CMP/GT Rm,Rn 0011nnnnmmmm0111
CMP/PL Rn
0100nnnn00010101
CMP/PZ Rn
0100nnnn00010001
CMP/STR Rm,Rn 0010nnnnmmmm1100
DIV1 Rm,Rn 0011nnnnmmmm0100
DIV0S Rm,Rn 0010nnnnmmmm0111
DIV0U
0000000000011001
DMULS.L Rm,Rn 0011nnnnmmmm1101
DMULU.L Rm,Rn 0011nnnnmmmm0101
Operation
Execution
States T Bit
Rn + Rm → Rn
1
—
Rn + imm → Rn
1
—
Rn + Rm + T → Rn, Carry 1
→T
Carry
Rn + Rm → Rn, Overflow 1
→T
Overflow
If R0 = imm, 1 → T
1
Comparison
result
If Rn = Rm, 1 → T
1
Comparison
result
If Rn≥Rm with unsigned 1
data, 1 → T
Comparison
result
If Rn ≥ Rm with signed 1
data, 1 → T
Comparison
result
If Rn > Rm with
1
unsigned data, 1 → T
Comparison
result
If Rn > Rm with signed 1
data, 1 → T
Comparison
result
If Rn > 0, 1 → T
1
Comparison
result
If Rn ≥ 0, 1 → T
1
Comparison
result
If Rn and Rm have an 1
equivalent byte, 1 → T
Comparison
result
Single-step division
1
(Rn ÷ Rm)
Calculation
result
MSB of Rn → Q, MSB 1
of Rm → M, M ^ Q → T
Calculation
result
0 → M/Q/T
1
0
Signed operation of Rn 2 to 4* —
× Rm → MACH, MACL
32 × 32 → 64 bits
Unsigned operation of 2 to 4* —
Rn × Rm → MACH, MACL
32 × 32 → 64 bits
Rev.4.00 Mar. 27, 2008 Page 38 of 882
REJ09B0108-0400