HD64F7144F50V Datasheet, PDF (710/932 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

19. Flash Memory (F-ZTAT Version)
19.4 Input/Output Pins
The flash memory is controlled by means of the pins shown in table 19.2.
Table 19.2 Pin Configuration
Pin Name
I/O
Function
RES
Input
Reset
FWP*¹
Input
Flash programming/erasing protection by hardware
MD1
Input
Sets this LSI's operating mode
MD0
Input
Sets this LSI's operating mode
TxD1 (PA4)*²
Output
Serial transmit data output
RxD1 (PA3)*²
Input
Serial receive data input
Notes: 1. Protection cannot be made to flash memory programming/erasing regardless of the
setting of the FWP pin when using E10A (when DBGMD is high)
2. In boot mode, SCI pins are fixed, and PA3 and PA4 pins are used as SCI pins.
Rev.4.00 Mar. 27, 2008 Page 664 of 882
REJ09B0108-0400