HD64F7144F50V Datasheet, PDF (463/932 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CKS1
0
0
1
1
SMR Setting
CKS0
0
1
0
1
13. Serial Communication Interface (SCI)
n
0
1
2
3
SMR Setting
BCP1
BCP0
S
0
0
32
0
1
64
1
0
372
1
1
256
Table 13.3 shows sample N settings in BRR in normal asynchronous mode. Table 13.4 shows the
maximum bit rate for each frequency in normal asynchronous mode. Table 13.6 shows sample N
settings in BRR in clocked synchronous mode. Table 13.8 shows sample N settings in BRR in
smart card interface mode. Table 13.9 shows the maximum bit rate for each frequency in smart
card interface mode. For details, refer to section 13.4.2, Receive Data Sampling Timing and
Reception Margin in Asynchronous Mode and section 13.7.4, Receive Data Sampling Timing and
Reception Margin. Tables 13.5 and 13.7 show the maximum bit rates with external clock input.
Rev.4.00 Mar. 27, 2008 Page 417 of 882
REJ09B0108-0400