HD64F7144F50V Datasheet, PDF (225/932 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

10. Direct Memory Access Controller (DMAC)
Bit Bit Name Initial Value R/W Description
1
NMIF
0
R/(W)* NMI Flag
Indicates input of an NMI. This bit is set irrespective
of whether the DMAC is operating or suspended. If
this bit is set during a data transfer, transfers on all
channels are suspended. The CPU is unable to write
a 1 to the NMIF. Clearing is effected by a 0 write
after 1 read.
0: No NMI interrupt, DMA transfer enabled
[Clearing condition]
Write NMIF = 0 after reading NMIF = 1
1: NMI has occurred, DMA transfer prohibited
[Setting condition]
NMI interrupt occurrence
0
DME
0
R/W
DMAC Master Enable
This bit enables activation of the entire DMAC. When
the DME bit and DE bit of the CHCR for the
corresponding channel are set to 1, that channel is
transfer-enabled. If this bit is cleared during a data
transfer, transfers on all channels are suspended.
0: Disable operation on all channels
1: Enable operation on all channels
Even when the DME bit is set, when the TE bit of the
CHCR is 1, or its DE bit is 0, transfer is disabled
when NMI of the DMAOR = 1 or when AE = 1.
Note: * Only 0 can be written to clear the flag.
Rev.4.00 Mar. 27, 2008 Page 179 of 882
REJ09B0108-0400