HD64F7144F50V Datasheet, PDF (227/932 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Figure 10.2 is a flowchart of this procedure.
10. Direct Memory Access Controller (DMAC)
Start
Initial settings
(SAR, DAR, DMATCR, CHCR, DMAOR)
DE, DME = 1 and
No
NMIF, AE, TE = 0?
Yes
Transfer request
No
occurs?*¹
Yes
Transfer (1 transfer unit);
DMATCR – 1 → DMATCR,
SAR and DAR updated
*²
Bus mode,
*³
transfer request mode,
DREQ detection selection
system
No
DMATCR = 0?
Yes
DEI interrupt request (when IE = 1)
Does
NMIF = 1, AE = 1,
No
DE = 0, or DME
= 0?
Yes
Transfer aborted
Does
NMIF = 1, AE = 1,
No
DE = 0, or DME
= 0?
Yes
Transfer ends
Normal end
Notes: 1. In auto-request mode, transfer begins when NMIF, AE, and TE are all 0,
and the DE and DME bits are set to 1.
2. DREQ = level detection in burst mode (external request) or cycle-steal
mode.
3. DREQ = edge detection in burst mode (external request), or auto-request
mode in burst mode.
Figure 10.2 DMAC Transfer Flowchart
Rev.4.00 Mar. 27, 2008 Page 181 of 882
REJ09B0108-0400