HD64F7144F50V Datasheet, PDF (837/932 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

26. Electrical Characteristics
26.3.13 H-UDI Timing
Table 26.15 shows H-UDI timing.
Table 26.15 H-UDI Timing
Conditions: V_CC = PLLV_CC =3.3 V ± 0.3 V, AV_CC = 3.3 V ± 0.3 V, AV_CC = V_CC ± 0.3 V,
AV_ref = 3.0 V to AV_CC , V_SS = PLLV_SS = AV_SS = 0 V, T_a = –20°C to +75°C
(regular specifications), T_a = –40°C to +85°C (wide-range specifications),
When programming or erasing flash memory, T_a = –20°C to +75°C.
Item
Symbol Min.
TCK clock cycle
t_tcyc
60*
TCK clock high-level width
t
0.4
TCKH
TCK clock low-level width
t
0.4
TCKL
TRST pulse width
t
20
TRSW
TRST setup time
t_TRSS
30
TMS setup time
t_TMSS
15
TMS hold time
t_TMSH
10
TDI setup time
t_TDIS
15
TDI hold time
t_TDIH
10
TDO delay time
t
⎯
TDOD
Note:
*
The value must not be under 2 × t .
cyc
Max.
500
0.6
0.6
⎯
⎯
⎯
⎯
⎯
⎯
30
Unit
ns
t
tcyc
t
tcyc
t
tcyc
ns
ns
ns
ns
ns
ns
Figure
Figure 26.24
Figure 26.25
Figure 26.26
TCK
t_TCKH
t_TCKL
V_IH
V_IH
V_IL
t_tcyc
V_IH
V_IL
Figure 26.24 H-UDI Clock Timing
Rev.4.00 Mar. 27, 2008 Page 791 of 882
REJ09B0108-0400