HD64F7144F50V Datasheet, PDF (184/932 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

9. Bus State Controller (BSC)
Figure 9.1 shows the BSC block diagram.
On-chip memory
control unit
WAIT
Wait control
unit
CS0 to CS7
Area control
unit
Bus interface
RAMER
WCR1
WCR2
BCR1
BCR2
RD
WRHH, WRHL
WRH, WRL
Memory control
unit
BSC
WCR1: Wait control register 1
WCR2: Wait control register 2
BCR1: Bus control register 1
BCR2: Bus control register 2
RAMER: RAM emulation register
Note: Refer to section 19, Flash Memory (F-ZTAT Version), for RAMER.
Pins CS4 to CS7 are available only for the masked ROM version and ROMless version.
Figure 9.1 BSC Block Diagram
Rev.4.00 Mar. 27, 2008 Page 138 of 882
REJ09B0108-0400