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B. Pin States of Bus Related Signals
Appendix B Pin States of Bus Related Signals
B. Pin States of Bus Related Signals
Table B.1 Pin States of Bus Related Signals (1)
On-chip Peripheral Module
Pin Name
On-chip ROM On-chip RAM
16-bit Space
Space
Space
8-bit Space _{Upper Byte Lower Byte Word/Longword}
CS0 to CS7 H
H
H
H
H
H
RD
RH
H
H
H
H
H
W⎯
H
H
H
H
H
WRHH R H
H
H
H
H
H
W⎯
H
H
H
H
H
WRHL R H
H
H
H
H
H
W⎯
H
H
H
H
H
WRH R H
H
H
H
H
H
W⎯
H
H
H
H
H
WRL R H
H
H
H
H
H
W⎯
H
H
H
H
H
A21 to A0
Address
Address
Address
Address
Address
Address
D31 to D24 Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
D23 to D16 Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
D15 to D8
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
D7 to D0
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
[Legend]
R:
W:
Enabled:
Read
Write
Chip select signals corresponding to accessed areas = Low
The other chip select signals = High
Rev.4.00 Mar. 27, 2008 Page 809 of 882
REJ09B0108-0400