HD64F7144F50V Datasheet, PDF (556/932 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

14. I²C Bus Interface (IIC) Option
Start
Set initial value
Set MST = 0 and TRS = 0 (ICCR)
Set ACKB = 0 (ICSR)
and HNDS = 1 (SCRX)
Clear the IRIC flag in ICCR
No
ICDRF = 1?
Yes
Read ICDR and clear IRIC
Read the IRIC flag in ICCR
No
IRIC = 1?
Yes
Clear the IRIC flag in ICCR
[1] Initial setting. Set slave receive mode.
[2] Read remained receive data.
[3] to [7] Wait for one byte to be received (slave address + R/W).
[8] Clear the IRIC flag.
Read AASX, AAS, and ADZ flags in ICSR
AAS = 1
Yes
and ADZ = 1?
No
Read the TRS bit in ICCR
Yes
TRS = 1?
No
General call address processing
* Description omitted
Slave transmit mode
Yes
Final reception?
No
Read ICDR
[10] Read receive data. The first read is a dummy read.
Read the IRIC flag in ICCR
No
IRIC = 1?
Yes
Clear the IRIC flag in ICCR
[5] to [7] Wait for completion of reception.
[8] Clear the IRIC flag.
Set ACKB = 1 (ICSR)
Read ICDR
Read the IRIC flag in ICCR
No
IRIC = 1?
Yes
Clear the IRIC flag in ICCR
End
[9] Set acknowledge data for the final reception.
[10] Read receive data.
[11] Detect stop condition.
[12] Clear the IRIC flag.
Figure 14.17 Example: Flowchart of Operations in the Slave Receive Mode (HNDS = 1)
Rev.4.00 Mar. 27, 2008 Page 510 of 882
REJ09B0108-0400