HD64F7144F50V Datasheet, PDF (63/932 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

2. CPU
2.2.2 Control Registers
The control registers consist of three 32-bit registers: status register (SR), global base register
(GBR), and vector base register (VBR). The status register indicates processing states. The global
base register functions as a base address for the indirect GBR addressing mode to transfer data to
the registers of on-chip peripheral modules. The vector base register functions as the base address
of the exception processing vector area (including interrupts).
Status Register (SR):
Bit Bit Name Initial Value R/W
31 to —
All 0
R/W
10
9
M
8
Q
Undefined R/W
Undefined R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Used by the DIV0U, DIV0S, and DIV1 instructions.
Used by the DIV0U, DIV0S, and DIV1 instructions.
Bit Bit Name Initial Value R/W
7
I3
1
R/W
6
I2
1
R/W
5
I1
1
R/W
4
I0
1
R/W
3, 2 —
All 0
R/W
1
S
0
T
Undefined R/W
Undefined R/W
Description
Interrupt mask bits.
Reserved
These bits are always read as 0. The write value
should always be 0.
S bit
Used by the MAC instruction.
T bit
The MOVT, CMP/cond, TAS, TST, BT (BT/S), BF
(BF/S), SETT, and CLRT instructions use the T bit to
indicate true (1) or false (0).
The ADDV, ADDC, SUBV, SUBC, DIV0U, DIV0S,
DIV1, NEGC, SHAR, SHAL, SHLR, SHLL, ROTR,
ROTL, ROTCR, and ROTCL instructions also use the
T bit to indicate carry/borrow or overflow/underflow.
Rev.4.00 Mar. 27, 2008 Page 17 of 882
REJ09B0108-0400