HD64F7144F50V Datasheet, PDF (141/932 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

6.6.2 Stack after Interrupt Exception Processing
Figure 6.4 shows the stack after interrupt exception processing.
6. Interrupt Controller (INTC)
Address
4n–8
4n–4
4n
PC^*1
SR
32 bits
32 bits
SP^*2
Notes: 1. PC: Start address of the next instruction (return destination instruction) after the executing
instruction
2. Always make sure that SP is a multiple of 4
Figure 6.4 Stack after Interrupt Exception Processing
Rev.4.00 Mar. 27, 2008 Page 95 of 882
REJ09B0108-0400