HD64F7144F50V Datasheet, PDF (110/932 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

5. Exception Processing
Exception Sources
Vector Numbers Vector Table Address Offset
Trap instruction (user vector)
32
H'00000080 to H'00000083
:
:
63
H'000000FC to H'000000FF
Interrupts IRQ0
64
H'00000100 to H'00000103
IRQ1
65
H'00000104 to H'00000107
IRQ2
66
H'00000108 to H'0000010B
IRQ3
67
H'0000010C to H'0000010F
IRQ4
68
H'00000110 to H'00000113
IRQ5
69
H'00000114 to H'00000117
IRQ6
70
H'00000118 to H'0000011B
IRQ7
71
On-chip peripheral module*²
72
H'0000011C to H'0000011F
H'00000120 to H'00000123
:
:
255
H'000003FC to H'000003FF
Notes: 1. Only in the F-ZTAT version.
2. The vector numbers and vector table address offsets for each on-chip peripheral
module interrupt are given in table 6.2.
Table 5.4 Calculating Exception Processing Vector Table Addresses
Exception Source
Vector Table Address Calculation
Resets
Vector table address = (vector table address offset)
= (vector number) × 4
Address errors, interrupts,
instructions
Vector table address = VBR + (vector table address offset)
= VBR + (vector number) × 4
Notes: 1. VBR: Vector base register
2. Vector table address offset: See table 5.3.
3. Vector number: See table 5.3.
Rev.4.00 Mar. 27, 2008 Page 64 of 882
REJ09B0108-0400