HD64F7144F50V Datasheet, PDF (103/932 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

4. Clock Pulse Generator
4.2 Function for Detecting Oscillator Halt
This CPG can detect a clock halt and automatically cause the timer pins to become high-
impedance when any system abnormality causes the oscillator to halt. That is, when a change of
EXTAL has not been detected, the high-current 6 pins (PE9/TIOC3B/SCK3/TRST*,
PE11/TIOC3D/RXD3/TDO*, PE12/TIOC4A/TXD3/TCK*, PE13/TIOC4B/MRES,
PE14/TIOC4C/DACK0, PE15/TIOC4D/DACK1/IRQOUT) can be set to high-impedance
regardless of PFC setting. Refer to section 17.1.11, High-Current Port Control Register (PPCR),
for more details.
Even in software standby mode, these 6 pins can be set to high-impedance regardless of PFC
setting. Refer to section 17.1.11, High-Current Port Control Register (PPCR), for more details.
These pins enter the normal state after software standby mode is released. When abnormalities that
halt the oscillator occur except in software standby mode, other LSI operations become undefined.
In this case, LSI operations, including these 6 pins, become undefined even when the oscillator
operation starts again.
In the case of using E10A, the high-impedance function is disabled when an oscillation stop is
detected, or when in software standby state for the three pins of PE9/TIOC3B/SCK3/TRST,
PE11/TIOC3D/RXD3/TDO, and PE12/TIOC4A/TxD3/TCK of the SH7145.
Note: * Only in the SH7145.
Rev.4.00 Mar. 27, 2008 Page 57 of 882
REJ09B0108-0400