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PIC18F44J50-I Datasheet, PDF (98/562 Pages) Microchip Technology – 28/44-Pin, Low-Power, High-Performance USB Microcontrollers
PIC18F46J50 FAMILY
6.4.3.1
FSR Registers and the INDF
Operand (INDF)
At the core of Indirect Addressing are three sets of
registers: FSR0, FSR1 and FSR2. Each represents a
pair of 8-bit registers, FSRnH and FSRnL. The four
upper bits of the FSRnH register are not used, so each
FSR pair holds a 12-bit value. This represents a value
that can address the entire range of the data memory
in a linear fashion. The FSR register pairs then serve as
pointers to data memory locations.
Indirect Addressing is accomplished with a set of INDF
operands, INDF0 through INDF2. These can be pre-
sumed as “virtual” registers: they are mapped in the
SFR space but are not physically implemented. Read-
ing or writing to a particular INDF register actually
accesses its corresponding FSR register pair. A read
from INDF1, for example, reads the data at the address
indicated by FSR1H:FSR1L. Instructions that use the
INDF registers as operands actually use the contents
of their corresponding FSR as a pointer to the instruc-
tion’s target. The INDF operand is just a convenient
way of using the pointer.
Because Indirect Addressing uses a full 12-bit address,
data RAM banking is not necessary. Thus, the current
contents of the BSR and the Access RAM bit have no
effect on determining the target address.
FIGURE 6-8:
INDIRECT ADDRESSING
Using an instruction with one of the
Indirect Addressing registers as the
operand....
ADDWF, INDF1, 1
...uses the 12-bit address stored in
the FSR pair associated with that
register....
FSR1H:FSR1L
7
07
0
xxxx1111 11001100
000h
100h
200h
300h
Bank 0
Bank 1
Bank 2
Bank 3
through
Bank 13
...to determine the data memory
location to be used in that operation.
In this case, the FSR1 pair contains
FCCh. This means the contents of
location FCCh will be added to that
of the W register and stored back in
FCCh.
E00h
F00h
FFFh
Bank 14
Bank 15
Data Memory
DS39931D-page 98
 2011 Microchip Technology Inc.