PIC18F44J50-I Datasheet, PDF (38/562 Pages) Microchip Technology – 28/44-Pin, Low-Power, High-Performance USB Microcontrollers

PIC18F46J50 FAMILY
3.2.3 EXTERNAL CLOCK INPUT
The EC and ECPLL Oscillator modes require an
external clock source to be connected to the OSC1 pin.
There is no oscillator start-up time required after a
Power-on Reset (POR) or after an exit from Sleep mode.
In the EC Oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. In the ECPLL
Oscillator mode, the PLL output divided by 4 is available
on the OSC2 pin This signal may be used for test pur-
poses or to synchronize other logic. Figure 3-3 displays
the pin connections for the EC Oscillator mode.
FIGURE 3-3:
EXTERNAL CLOCK INPUT
OPERATION (EC AND
ECPLL CONFIGURATION)
Clock from
Ext. System
FOSC/4
OSC1/CLKI
PIC18F46J50
OSC2/CLKO
3.2.4
PLL FREQUENCY MULTIPLIER
PIC18F46J50 family devices include a PLL circuit. This
is provided specifically for USB applications with lower
speed oscillators and can also be used as a
microcontroller clock source.
The PLL can be enabled in HSPLL, ECPLL,
INTOSCPLL and INTOSCPLLO Oscillator modes by
setting the PLLEN bit (OSCTUNE<6>). It is designed
to produce a fixed 96 MHz reference clock from a
fixed 4 MHz input. The output can then be divided and
used for both the USB and the microcontroller core
clock. Because the PLL has a fixed frequency input
and output, there are eight prescaling options to
match the oscillator input frequency to the PLL. This
prescaler allows the PLL to be used with crystals, res-
onators and external clocks, which are integer multiple
frequencies of 4 MHz. For example, a 12 MHz crystal
could be used in a Prescaler Divide-by-Three mode to
drive the PLL.
There is also a CPU divider, which can be used to derive
the microcontroller clock from the PLL. This allows the
USB peripheral and microcontroller to use the same
oscillator input and still operate at different clock speeds.
The CPU divider can reduce the incoming frequency by
a factor of 1, 2, 3 or 6.
3.2.5 INTERNAL OSCILLATOR BLOCK
The PIC18F46J50 family devices include an internal
oscillator block which generates two different clock
signals; either can be used as the microcontroller’s
clock source. The internal oscillator may eliminate the
need for external oscillator circuits on the OSC1 and/or
OSC2 pins.
The main output (INTOSC) is an 8 MHz clock source
which can be used to directly drive the device clock. It
also drives the INTOSC postscaler which can provide a
range of clock frequencies from 31 kHz to 8 MHz.
Additionally, the INTOSC may be used in conjunction
with the PLL to generate clock frequencies up to
48 MHz.
The other clock source is the internal RC oscillator
(INTRC) which provides a nominal 31 kHz output.
INTRC is enabled if it is selected as the device clock
source. It is also enabled automatically when any of the
following are enabled:
• Power-up Timer
• Fail-Safe Clock Monitor
• Watchdog Timer
• Two-Speed Start-up
These features are discussed in larger detail in
Section 27.0 “Special Features of the CPU”.
The clock source frequency (INTOSC direct, INTRC
direct or INTOSC postscaler) is selected by configuring
the IRCF bits of the OSCCON register (Page 43).
DS39931D-page 38
 2011 Microchip Technology Inc.