PIC18F44J50-I Datasheet, PDF(70/562 Page) Microchip Technology – 28/44-Pin, Low-Power, High-Performance USB Microcontrollers

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PIC18F44J50-I Datasheet, PDF (70/562 Pages) Microchip Technology – 28/44-Pin, Low-Power, High-Performance USB Microcontrollers

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PIC18F46J50 FAMILY

TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

Register

Applicable Devices

Power-on Reset,

Brown-out Reset,

Wake From Deep

Sleep

MCLR Resets

WDT Reset

RESET Instruction

Stack Resets

CM Resets

Wake-up via WDT

or Interrupt

INDF2

PIC18F2XJ50 PIC18F4XJ50

N/A

N/A

N/A

POSTINC2

PIC18F2XJ50 PIC18F4XJ50

N/A

N/A

N/A

POSTDEC2 PIC18F2XJ50 PIC18F4XJ50

N/A

N/A

N/A

PREINC2

PIC18F2XJ50 PIC18F4XJ50

N/A

N/A

N/A

PLUSW2

PIC18F2XJ50 PIC18F4XJ50

N/A

N/A

N/A

FSR2H

PIC18F2XJ50 PIC18F4XJ50

---- 0000

---- 0000

---- uuuu

FSR2L

PIC18F2XJ50 PIC18F4XJ50

xxxx xxxx

uuuu uuuu

uuuu uuuu

STATUS

PIC18F2XJ50 PIC18F4XJ50

---x xxxx

---u uuuu

---u uuuu

TMR0H

PIC18F2XJ50 PIC18F4XJ50

0000 0000

0000 0000

uuuu uuuu

TMR0L

PIC18F2XJ50 PIC18F4XJ50

xxxx xxxx

uuuu uuuu

uuuu uuuu

T0CON

PIC18F2XJ50 PIC18F4XJ50

1111 1111

1111 1111

uuuu uuuu

OSCCON

PIC18F2XJ50 PIC18F4XJ50

0110 q100

0110 q100

uuuu q1uu

CM1CON

PIC18F2XJ50 PIC18F4XJ50

0001 1111

0001 1111

uuuu uuuu

CM2CON

PIC18F2XJ50 PIC18F4XJ50

0001 1111

0001 1111

uuuu uuuu

RCON(4)

PIC18F2XJ50 PIC18F4XJ50

0-11 11qq

0-qq qquu

u-qq qquu

TMR1H

PIC18F2XJ50 PIC18F4XJ50

xxxx xxxx

uuuu uuuu

uuuu uuuu

TMR1L

PIC18F2XJ50 PIC18F4XJ50

xxxx xxxx

uuuu uuuu

uuuu uuuu

T1CON

PIC18F2XJ50 PIC18F4XJ50

0000 0000

uuuu uuuu

uuuu uuuu

TMR2

PIC18F2XJ50 PIC18F4XJ50

0000 0000

0000 0000

uuuu uuuu

PR2

PIC18F2XJ50 PIC18F4XJ50

1111 1111

1111 1111

uuuu uuuu

T2CON

PIC18F2XJ50 PIC18F4XJ50

-000 0000

-000 0000

-uuu uuuu

SSP1BUF

PIC18F2XJ50 PIC18F4XJ50

xxxx xxxx

uuuu uuuu

uuuu uuuu

SSP1ADD

PIC18F2XJ50 PIC18F4XJ50

0000 0000

0000 0000

uuuu uuuu

SSP1MSK

PIC18F2XJ50 PIC18F4XJ50

1111 1111

1111 1111

uuuu uuuu

SSP1STAT

PIC18F2XJ50 PIC18F4XJ50

0000 0000

0000 0000

uuuu uuuu

SSP1CON1 PIC18F2XJ50 PIC18F4XJ50

0000 0000

0000 0000

uuuu uuuu

SSP1CON2 PIC18F2XJ50 PIC18F4XJ50

0000 0000

0000 0000

uuuu uuuu

ADRESH

PIC18F2XJ50 PIC18F4XJ50

xxxx xxxx

uuuu uuuu

uuuu uuuu

ADRESL

PIC18F2XJ50 PIC18F4XJ50

xxxx xxxx

uuuu uuuu

uuuu uuuu

ADCON0

PIC18F2XJ50 PIC18F4XJ50

0000 0000

0000 0000

uuuu uuuu

ADCON1

PIC18F2XJ50 PIC18F4XJ50

0000 0000

0000 0000

uuuu uuuu

WDTCON

PIC18F2XJ50 PIC18F4XJ50

1qq- q000

1qq- 0000

uqq- uuuu

Legend:

Note 1:

u = unchanged, x = unknown, - = unimplemented bit, read as â0â, q = value depends on condition.

When the wake-up is due to an interrupt and the GIEH (and GIEL if low priority) bit(s) are set, the TOSU,

TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the

next location in the hardware stack.

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt

vector (0008h or 0018h).

3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

4: See Table 5-1 for Reset value for specific condition.

5: Not implemented on PIC18F2XJ50 devices.

6: Not implemented on âLFâ devices.

DS39931D-page 70

ï£ 2011 Microchip Technology Inc.

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