PIC18F44J50-I Datasheet, PDF (50/562 Pages) Microchip Technology – 28/44-Pin, Low-Power, High-Performance USB Microcontrollers

PIC18F46J50 FAMILY
4.2.3 RC_RUN MODE
In RC_RUN mode, the CPU and peripherals are
clocked from the internal oscillator; the primary clock is
shut down. This mode provides the best power conser-
vation of all the Run modes while still executing code.
It works well for user applications, which are not highly
timing-sensitive or do not require high-speed clocks at
all times.
This mode is entered by setting the SCS<1:0> bits
(OSCCON<1:0>) to ‘11’. When the clock source is
switched to the internal oscillator block (see
Figure 4-3), the primary oscillator is shutdown and the
OSTS bit is cleared.
On transitions from RC_RUN mode to PRI_RUN mode,
the device continues to be clocked from the INTOSC
block while the primary clock is started. When the
primary clock becomes ready, a clock switch to the
primary clock occurs (see Figure 4-4). When the clock
switch is complete, the OSTS bit is set and the primary
clock is providing the device clock. The IDLEN and
SCS bits are not affected by the switch. The INTRC
clock source will continue to run if either the WDT or the
FSCM is enabled.
FIGURE 4-3:
TRANSITION TIMING TO RC_RUN MODE
Q1 Q2 Q3 Q4 Q1
INTRC
1
OSC1
CPU
Clock
Peripheral
Clock
Program
Counter
PC
2
3
n-1 n
Clock Transition
PC + 2
Q2 Q3 Q4 Q1 Q2 Q3
PC + 4
FIGURE 4-4:
TRANSITION TIMING FROM RC_RUN MODE TO PRI_RUN MODE
INTRC
Q1
Q2
Q3
Q4
Q1
Q2 Q3 Q4 Q1 Q2 Q3
OSC1
PLL Clock
Output
TOST⁽¹⁾
CPU Clock
Peripheral
Clock
Program
Counter
PC
SCS<1:0> Bits Changed
TPLL⁽¹⁾
OSTS Bit Set
1 2 n-1 n
Clock
Transition
PC + 2
Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
PC + 4
DS39931D-page 50
 2011 Microchip Technology Inc.