PIC18F44J50-I Datasheet, PDF (274/562 Pages) Microchip Technology – 28/44-Pin, Low-Power, High-Performance USB Microcontrollers

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19.3.4 ENABLING SPI I/O
To enable the serial port, MSSP Enable bit, SSPEN
(SSPxCON1<5>), must be set. To reset or reconfigure
SPI mode, clear the SSPEN bit, reinitialize the
SSPxCON1 registers and then set the SSPEN bit. This
configures the SDIx, SDOx, SCKx and SSx pins as
serial port pins. For the pins to behave as the serial port
function, the appropriate TRIS bits, ANCON/PCFG bits
and Peripheral Pin Select registers (if using MSSP2)
should be correctly initialized prior to setting the
SSPEN bit.
A typical SPI serial port initialization process follows:
• Initialize ODCON3 register (optional open-drain
output control)
• Initialize remappable pin functions (if using
MSSP2, see Section 10.7 “Peripheral Pin
Select (PPS)”)
• Initialize SCKx LAT value to desired Idle SCK
level (if master device)
• Initialize SCKx ANCON/PCFG bit (if Slave mode
and multiplexed with ANx function)
• Initialize SCKx TRIS bit as output (Master mode)
or input (Slave mode)
• Initialize SDIx ANCON/PCFG bit (if SDIx is
multiplexed with ANx function)
• Initialize SDIx TRIS bit
• Initialize SSx ANCON/PCFG bit (if Slave mode
and multiplexed with ANx function)
• Initialize SSx TRIS bit (Slave modes)
• Initialize SDOx TRIS bit
• Initialize SSPxSTAT register
• Initialize SSPxCON1 register
• Set SSPEN bit to enable the module
Any MSSP1 serial port function that is not desired may
be overridden by programming the corresponding Data
Direction (TRIS) register to the opposite value. If
individual MSSP2 serial port functions will not be used,
they may be left unmapped.
Note:
When MSSP2 is used in SPI Master
mode, the SCK2 function must be config-
ured as both an output and an input in the
PPS module. SCK2 must be initialized as
an output pin (by writing 0x0A to one of
the RPORx registers). Additionally,
SCK2IN must also be mapped to the
same pin by initializing the RPINR22 reg-
ister. Failure to initialize SCK2/SCK2IN as
both output and input will prevent the
module from receiving data on the SDI2
pin, as the module uses the SCK2IN
signal to latch the received data.
19.3.5 TYPICAL CONNECTION
Figure 19-2 illustrates a typical connection between two
microcontrollers. The master controller (Processor 1)
initiates the data transfer by sending the SCKx signal.
Data is shifted out of both shift registers on their pro-
grammed clock edge and latched on the opposite edge
of the clock. Both processors should be programmed to
the same Clock Polarity (CKP), then both controllers
would send and receive data at the same time. Whether
the data is meaningful (or dummy data) depends on the
application software. This leads to three scenarios for
data transmission:
• Master sends valid data–Slave sends dummy
data
• Master sends valid data–Slave sends valid data
• Master sends dummy data–Slave sends valid data
FIGURE 19-2:
SPI MASTER/SLAVE CONNECTION
SPI Master SSPM<3:0> = 00xxb
SDOx
SPI Slave SSPM<3:0> = 010xb
SDIx
Serial Input Buffer
(SSPxBUF)
Serial Input Buffer
(SSPxBUF)
Shift Register
(SSPxSR)
MSb
LSb
SDIx
PROCESSOR 1
SCKx
Serial Clock
SDOx
Shift Register
(SSPxSR)
MSb
LSb
SCKx
PROCESSOR 2
DS39931D-page 274
 2011 Microchip Technology Inc.