PIC18F44J50-I Datasheet, PDF (92/562 Pages) Microchip Technology – 28/44-Pin, Low-Power, High-Performance USB Microcontrollers

PIC18F46J50 FAMILY
TABLE 6-4: REGISTER FILE SUMMARY (PIC18F46J50 FAMILY) (CONTINUED)
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on Details
POR, BOR on Page:
T3GCON
TMR3GE T3GPOL
T3GTM
T3GSPM
T3GGO/
T3DONE
T3GVAL
T3GSS1 T3GSS0 0000 0x00 72, 214
TRISE
—
—
—
—
—
TRISE2
TRISE1
TRISE0 ---- -111 72
TRISD
TRISD7 TRISD6 TRISD5 TRISD4
TRISD3
TRISD2
TRISD1
TRISD0 1111 1111 72, 146
TRISC
TRISC7 TRISC6
—
—
—
TRISC2
TRISC1
TRISC0 11-- -111 72, 143
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0 1111 1111 72, 139
TRISA
TRISA7⁽⁷⁾ TRISA6⁽⁷⁾ TRISA5
—
TRISA3
TRISA2
TRISA1
TRISA0 qq1- 1111 72, 136
ALRMCFG
ALRMEN CHIME AMASK3 AMASK2 AMASK1
AMASK0 ALRMPTR1 ALRMPTR0 0000 0000 72, 229
ALRMRPT
ARPT7
ARPT6
ARPT5
ARPT4
ARPT3
ARPT2
ARPT1
ARPT0 0000 0000 72, 230
ALRMVALH Alarm Value Register Window High Byte, Based on ALRMPTR<1:0>
xxxx xxxx 72, 234
ALRMVALL Alarm Value Register Window Low Byte, Based on ALRMPTR<1:0>
xxxx xxxx 72, 234
LATE
—
—
—
—
—
LATE2
LATE1
LATE0 ---- -xxx 72, 149
LATD
LATD7
LATD6
LATD5
LATD4
LATD3
LATD2
LATD1
LATD0 xxxx xxxx 72, 147
LATC
LATC7
LATC6
—
—
—
LATC2
LATC1
LATC0 xxxx -xxx 72, 142
LATB
LATB7
LATB6
LATB5
LATB4
LATB3
LATB2
LATB1
LATB0 xxxx xxxx 72, 142
LATA
LATA7
LATA6
LATA5
—
LATA3
LATA2
LATA1
LATA0 xxx- xxxx 72, 142
DMACON1
SSCON1 SSCON0 TXINC
RXINC
DUPLEX1 DUPLEX0 DLYINTEN DMAEN 0000 0000 72, 282
DMATXBUF SPI DMA Transmit Buffer
xxxx xxxx 72
DMACON2
DLYCYC3 DLYCYC2 DLYCYC1 DLYCYC0 INTLVL3
INTLVL2
INTLVL1 INTLVL0 0000 0000 72, 283
HLVDCON
VDIRMAG BGVST
IRVST
HLVDEN
HLVDL3
HLVDL2
HLVDL1 HLVDL0 0000 0000 72
PORTE
RDPU
REPU
—
—
—
RE2
RE1
RE0 00-- -xxx 72, 132
PORTD
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0 xxxx xxxx 72, 132
PORTC
RC7
RC6
RC5
RC4
—
RC2
RC1
RC0 xxxx -xxx 72, 132
PORTB
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0 xxxx xxxx 72, 132
PORTA
RA7
RA6
RA5
—
RA3
RA2
RA1
RA0 xxx- xxxx 72, 356
SPBRGH1
EUSART1 Baud Rate Generator Register High Byte
0000 0000 72, 327
BAUDCON1
ABDOVF RCIDL
RXDTP
TXCKP
BRG16
—
WUE
ABDEN 0100 0-00 72, 327
SPBRGH2
EUSART2 Baud Rate Generator Register High Byte
0000 0000 72, 327
BAUDCON2
ABDOVF RCIDL
RXDTP
TXCKP
BRG16
—
WUE
ABDEN 0100 0-00 72, 327
TMR3H
Timer3 Register High Byte
xxxx xxxx 73, 197
TMR3L
Timer3 Register Low Byte
xxxx xxxx 73, 197
T3CON
TMR3CS1 TMR3CS0 T3CKPS1 T3CKPS0 T3OSCEN T3SYNC
RD16
TMR3ON 0000 0000 73, 197
TMR4
Timer4 Register
0000 0000 73, 223
PR4
Timer4 Period Register
1111 1111 73, 197
T4CON
—
T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0 -000 0000 73, 223
SSP2BUF
SSP2ADD/
SSP2MSK⁽⁴⁾
MSSP2 Receive Buffer/Transmit Register
MSSP2 Address Register (I²C™ Slave mode), MSSP2 Baud Rate Reload Register (I²C Master mode)
MSK7
MSK6
MSK5
MSK4
MSK3
MSK2
MSK1
MSK0
xxxx xxxx 73, 288,
322
0000 0000 73, 288
1111 1111 73, 295
SSP2STAT
SMP
CKE
D/A
P
S
R/W
UA
BF
0000 0000 73, 270,
310
SSP2CON1
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0 0000 0000 73, 270,
322
Legend:
Note 1:
2:
3:
4:
5:
6:
7:
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved. Bold indicates shared access SFRs.
Bit 21 of the PC is only available in Serial Programming (SP) modes.
Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled.
The SSPxMSK registers are only accessible when SSPxCON2<3:0> = 1001.
Alternate names and definitions for these bits when the MSSP module is operating in I²C™ Slave mode. See Section 19.5.3.2 “Address
Masking Modes” for details.
These bits and/or registers are only available on 44-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset values are
shown for 44-pin devices.
The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the same physical registers and addresses, but have
different functions determined by the module’s operating mode. See Section 11.1.2 “Data Registers” for more information.
The TRISA6 and TRISA7 bits are only implemented when the pins are not configured for primary oscillator functions.
DS39931D-page 92
 2011 Microchip Technology Inc.