PIC18F44J50-I Datasheet, PDF(207/562 Page) Microchip Technology – 28/44-Pin, Low-Power, High-Performance USB Microcontrollers

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PIC18F44J50-I Datasheet, PDF (207/562 Pages) Microchip Technology – 28/44-Pin, Low-Power, High-Performance USB Microcontrollers

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PIC18F46J50 FAMILY

13.7 Resetting Timer1 Using the ECCP

Special Event Trigger

If ECCP1 or ECCP2 is configured to use Timer1 and to

generate a Special Event Trigger in Compare mode

(CCPxM<3:0> = 1011), this signal will reset Timer3.

The trigger from ECCP2 will also start an A/D conver-

sion if the A/D module is enabled (see Section 18.3.4

âSpecial Event Triggerâ for more information).

The module must be configured as either a timer or a

synchronous counter to take advantage of this feature.

When used this way, the CCPRxH:CCPRxL register

pair effectively becomes a Period register for Timer1.

If Timer1 is running in Asynchronous Counter mode,

this Reset operation may not work.

In the event that a write to Timer1 coincides with a

Special Event Trigger, the write operation will take

precedence.

Note:

The Special Event Trigger from the

ECCPx module will not set the TMR1IF

interrupt flag bit (PIR1<0>).

13.8 Timer1 Gate

The Timer1 can be configured to count freely or the count

can be enabled and disabled using the Timer1 gate

circuitry. This is also referred to as Timer1 gate count

enable.

Timer1 gate can also be driven by multiple selectable

sources.

13.8.1 TIMER1 GATE COUNT ENABLE

The Timer1 Gate Enable mode is enabled by setting

the TMR1GE bit of the T1GCON register. The polarity

of the Timer1 Gate Enable mode is configured using

the T1GPOL bit of the T1GCON register.

When Timer1 Gate Enable mode is enabled, Timer1

will increment on the rising edge of the Timer1 clock

source. When Timer1 Gate Enable mode is disabled,

no incrementing will occur and Timer1 will hold the

current count. See Figure 13-4 for timing details.

TABLE 13-3: TIMER1 GATE ENABLE

SELECTIONS

T1CLK T1GPOL T1G Timer1 Operation

ï

0

0 Counts

ï

0

1 Holds Count

ï

1

0 Holds Count

ï

1

1 Counts

FIGURE 13-4:

TIMER1 GATE COUNT ENABLE MODE

TMR1GE

T1GPOL

T1G_IN

T1CKI

T1GVAL

Timer1

N

N+1

N+2

N+3 N+4

ï£ 2011 Microchip Technology Inc.

DS39931D-page 207

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