PIC18F44J50-I Datasheet, PDF (351/562 Pages) Microchip Technology – 28/44-Pin, Low-Power, High-Performance USB Microcontrollers

PIC18F46J50 FAMILY
After the A/D module has been configured as desired,
the selected channel must be acquired before the
conversion is started. The analog input channels must
have their corresponding TRIS bits selected as an
input. To determine acquisition time, see Section 21.1
“A/D Acquisition Requirements”. After this acquisi-
tion time has elapsed, the A/D conversion can be
started. An acquisition time can be programmed to
occur between setting the GO/DONE bit and the actual
start of the conversion.
The following steps should be followed to do an A/D
conversion:
1. Configure the A/D module:
• Configure the required ADC pins as analog
pins using ANCON0, ANCON1
• Set voltage reference using ADCON0
• Select A/D input channel (ADCON0)
• Select A/D acquisition time (ADCON1)
• Select A/D conversion clock (ADCON1)
• Turn on A/D module (ADCON0)
2. Configure the A/D interrupt (if desired):
• Clear ADIF bit
• Set ADIE bit
• Set GIE bit
3. Wait the required acquisition time (if required).
4. Start conversion:
• Set GO/DONE bit (ADCON0<1>)
5. Wait for the A/D conversion to complete, by either:
• Polling for the GO/DONE bit to be cleared
OR
• Waiting for the A/D interrupt
6. Read A/D Result registers (ADRESH:ADRESL);
clear bit, ADIF, if required.
7. For next conversion, go to Step 1 or Step 2, as
required. The A/D conversion time per bit is
defined as TAD. A minimum Wait of 2 TAD is
required before the next acquisition starts.
FIGURE 21-2:
ANALOG INPUT MODEL
VDD
RS ^ANx
VT = 0.6V
RIC 1k
Sampling
Switch
SS _RSS
VAIN
CPIN
5 pF
VT = 0.6V
ILEAKAGE
±100 nA
Legend: CPIN
VT
ILEAKAGE
RIC
SS
CHOLD
RSS
= Input Capacitance
= Threshold Voltage
= Leakage Current at the pin due to
various junctions
= Interconnect Resistance
= Sampling Switch
= Sample/Hold Capacitance (from DAC)
= Sampling Switch Resistance
CHOLD = 25 pF
VSS
VDD
1 23 4
Sampling Switch (k)
 2011 Microchip Technology Inc.
DS39931D-page 351