PIC18F44J50-I Datasheet, PDF (59/562 Pages) Microchip Technology – 28/44-Pin, Low-Power, High-Performance USB Microcontrollers

PIC18F46J50 FAMILY
REGISTER 4-5:
U-0
—
bit 7
DSWAKEH: DEEP SLEEP WAKE HIGH BYTE REGISTER (BANKED F4Bh)
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
—
—
—
—
—
—
DSINT0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-1
bit 0
Unimplemented: Read as ‘0’
DSINT0: Interrupt-on-Change bit
1 = Interrupt-on-change was asserted during Deep Sleep
0 = Interrupt-on-change was not asserted during Deep Sleep
REGISTER 4-6:
R/W-0
DSFLT
bit 7
DSWAKEL: DEEP SLEEP WAKE LOW BYTE REGISTER (BANKED F4Ah)
U-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
R/W-1
—
DSULP
DSWDT
DSRTC
DSMCLR
—
DSPOR
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
DSFLT: Deep Sleep Fault Detected bit
1 = A Deep Sleep Fault was detected during Deep Sleep
0 = A Deep Sleep Fault was not detected during Deep Sleep
bit 6
Unimplemented: Read as ‘0’
bit 5
DSULP: Ultra Low-Power Wake-up Status bit
1 = An Ultra Low-Power Wake-up event occurred during Deep Sleep
0 = An Ultra Low-Power Wake-up event did not occur during Deep Sleep
bit 4
DSWDT: Deep Sleep Watchdog Timer Time-out bit
1 = The Deep Sleep Watchdog Timer timed out during Deep Sleep
0 = The Deep Sleep Watchdog Timer did not time out during Deep Sleep
bit 3
DSRTC: Real-Time Clock and Calendar Alarm bit
1 = The Real-Time Clock/Calendar triggered an alarm during Deep Sleep
0 = The Real-Time Clock /Calendar did not trigger an alarm during Deep Sleep
bit 2
DSMCLR: MCLR Event bit
1 = The MCLR pin was asserted during Deep Sleep
0 = The MCLR pin was not asserted during Deep Sleep
bit 1
Unimplemented: Read as ‘0’
bit 0
DSPOR: Power-on Reset Event bit
1 = The VDD supply POR circuit was active and a POR event was detected⁽¹⁾
0 = The VDD supply POR circuit was not active, or was active, but did not detect a POR event
Note 1: Unlike the other bits in this register, this bit can be set outside of Deep Sleep.
 2011 Microchip Technology Inc.
DS39931D-page 59