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| PIC18F44J50-I Datasheet, PDF (279/562 Pages) Microchip Technology – 28/44-Pin, Low-Power, High-Performance USB Microcontrollers | |||
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PIC18F46J50 FAMILY
TABLE 19-2: REGISTERS ASSOCIATED WITH SPI OPERATION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on Page:
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE
RBIE TMR0IF INT0IF
RBIF
69
PIR1
PIE1
IPR1
PMPIF(2) ADIF
RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF
72
PMPIE(2) ADIE
RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE
72
PMPIP(2) ADIP
RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP
72
PIR3
SSP2IF BCL2IF RC2IF TX2IF TMR4IF CTMUIF TMR3GIF RTCCIF
72
PIE3
SSP2IE BCL2IE RC2IE TX2IE TMR4IE CTMUIE TMR3GIE RTCCIE
72
IPR3
SSP2IP BCL2IP RC2IP TX2IP TMR4IP CTMUIP TMR3GIP RTCCIP
72
TRISA
TRISA7 TRISA6 TRISA5
â
TRISA3 TRISA2 TRISA1 TRISA0
72
TRISB
TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0
72
TRISC
TRISC7 TRISC6
â
â
â
TRISC2 TRISC1 TRISC0
72
SSP1BUF MSSP1 Receive Buffer/Transmit Register
70
SSPxCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0
70
SSPxSTAT SMP
CKE
D/A
P
S
R/W
UA
BF
70
SSP2BUF MSSP2 Receive Buffer/Transmit Register
73
ODCON3(1)
â
â
â
â
â
â
SPI2OD SPI1OD
74
Legend: Shaded cells are not used by the MSSP module in SPI mode.
Note 1: Configuration SFR overlaps with default SFR at this address; available only when WDTCON<4> = 1.
2: These bits are only available on 44-pin devices.
ï£ 2011 Microchip Technology Inc.
DS39931D-page 279
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