PIC18F44J50-I Datasheet, PDF (436/562 Pages) Microchip Technology – 28/44-Pin, Low-Power, High-Performance USB Microcontrollers

PIC18F46J50 FAMILY
TABLE 28-1: OPCODE FIELD DESCRIPTIONS
Field
a
bbb
BSR
C, DC, Z, OV, N
d
dest
f
f_s
f_d
GIE
k
label
mm
*
*+
*-
+*
n
PC
PCL
PCH
PCLATH
PCLATU
PD
PRODH
PRODL
s
TBLPTR
TABLAT
TO
TOS
u
WDT
WREG
x
z_s
z_d
{}
[text]
(text)
[expr]<n>

<>

italics
Description
RAM access bit:
a = 0: RAM location in Access RAM (BSR register is ignored)
a = 1: RAM bank is specified by BSR register
Bit address within an 8-bit file register (0 to 7)
Bank Select Register. Used to select the current RAM bank
ALU Status bits: Carry, Digit Carry, Zero, Overflow, Negative
Destination select bit:
d = 0: store result in WREG
d = 1: store result in file register f
Destination: either the WREG register or the specified register file location
8-bit register file address (00h to FFh), or 2-bit FSR designator (0h to 3h)
12-bit register file address (000h to FFFh). This is the source address
12-bit register file address (000h to FFFh). This is the destination address
Global Interrupt Enable bit
Literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value)
Label name
The mode of the TBLPTR register for the table read and table write instructions
Used only with table read and table write instructions
No Change to register (such as TBLPTR with table reads and writes)
Post-Increment register (such as TBLPTR with table reads and writes)
Post-Decrement register (such as TBLPTR with table reads and writes)
Pre-Increment register (such as TBLPTR with table reads and writes)
The relative address (2’s complement number) for relative branch instructions or the direct address for
Call/Branch and Return instructions
Program Counter
Program Counter Low Byte
Program Counter High Byte
Program Counter High Byte Latch
Program Counter Upper Byte Latch
Power-Down bit
Product of Multiply High Byte
Product of Multiply Low Byte
Fast Call/Return mode select bit:
s = 0: do not update into/from shadow registers
s = 1: certain registers loaded into/from shadow registers (Fast mode)
21-Bit Table Pointer (points to a program memory location)
8-Bit Table Latch
Time-out bit
Top-of-Stack
Unused or Unchanged
Watchdog Timer
Working register (accumulator)
Don’t care (‘0’ or ‘1’). The assembler will generate code with x = 0; it is the recommended form of use for
compatibility with all Microchip software tools
7-bit offset value for Indirect Addressing of register files (source)
7-bit offset value for Indirect Addressing of register files (destination)
Optional argument
Indicates Indexed Addressing
The contents of text
Specifies bit n of the register indicated by the pointer, expr
Assigned to
Register bit field
In the set of
User-defined term (font is Courier New)
DS39931D-page 436
 2011 Microchip Technology Inc.