PIC18F44J50-I Datasheet, PDF (510/562 Pages) Microchip Technology – 28/44-Pin, Low-Power, High-Performance USB Microcontrollers

PIC18F46J50 FAMILY
30.4.3 TIMING DIAGRAMS AND SPECIFICATIONS
FIGURE 30-5:
EXTERNAL CLOCK TIMING
Q4
Q1
Q2
Q3
OSC1
CLKO
1
3
3
2
Q4
Q1
4
4
TABLE 30-10: EXTERNAL CLOCK TIMING REQUIREMENTS
Param.
No.
Symbol
Characteristic
Min
Max Units
Conditions
1A
FOSC
External CLKI Frequency⁽¹⁾
DC
48
MHz EC Oscillator mode
DC
48
ECPLL Oscillator mode⁽²⁾
Oscillator Frequency⁽¹⁾
4
16
MHz HS Oscillator mode
4
16⁽⁴⁾
HSPLL Oscillator mode⁽³⁾
1
TOSC
External CLKI Period⁽¹⁾
20.8
—
ns EC Oscillator mode
20.8
—
ECPLL Oscillator mode⁽²⁾
Oscillator Period⁽¹⁾
62.5
250
ns HS Oscillator mode
62.5⁽⁴⁾
250
HSPLL Oscillator mode⁽³⁾
2
TCY
Instruction Cycle Time⁽¹⁾
83.3
DC
ns TCY = 4/FOSC, Industrial
3
TOSL,
External Clock in (OSC1)
10
TOSH
High or Low Time
—
ns EC Oscillator mode
4
TOSR, External Clock in (OSC1)
—
TOSF
Rise or Fall Time
7.5
ns EC Oscillator mode
Note 1:
The instruction cycle period (TCY) equals four times the input oscillator time base period for all configura-
tions except PLL. All specified values are based on characterization data for that particular oscillator type
under standard operating conditions, with the device executing code. Exceeding these specified limits may
result in an unstable oscillator operation and/or higher than expected current consumption. All devices are
tested to operate at “min.” values with an external clock applied to the OSC1/CLKI pin. When an external
clock input is used, the “max.” cycle time limit is “DC” (no clock) for all devices.
2: In order to use the PLL, the external clock frequency must be either 4, 8, 12, 16, 20, 24, 40 or 48 MHz.
3: In order to use the PLL, the crystal/resonator must produce a frequency of either 4, 8, 12 or 16 MHz.
4: This is the maximum crystal/resonator driver frequency. The internal FOSC frequency when running from
the PLL can be up to 48 MHz.
DS39931D-page 510
 2011 Microchip Technology Inc.