PIC18F44J50-I Datasheet, PDF (148/562 Pages) Microchip Technology – 28/44-Pin, Low-Power, High-Performance USB Microcontrollers

PIC18F46J50 FAMILY
10.6 PORTE, TRISE and LATE
Registers
Note: PORTE is available only on 44-pin devices.
Depending on the particular PIC18F46J50 family
device selected, PORTE is implemented in two
different ways.
For 44-pin devices, PORTE is a 3-bit wide port. Three
pins (RE0/AN5/PMRD, RE1/AN6/PMWR and RE2/
AN7/PMCS) are individually configurable as inputs or
outputs. These pins have Schmitt Trigger input buffers.
When selected as analog inputs, these pins will read as
‘0’s.
The corresponding Data Direction register is TRISE.
Setting a TRISE bit (= 1) will make the corresponding
PORTE pin an input (i.e., put the corresponding output
driver in a High-Impedance mode). Clearing a TRISE
bit (= 0) will make the corresponding PORTE pin an
output (i.e., put the contents of the output latch on the
selected pin).
TRISE controls the direction of the RE pins, even when
they are being used as analog inputs. The user must
make sure to keep the pins configured as inputs when
using them as analog inputs.
Note: On a POR, RE<2:0> are configured as
analog inputs.
REGISTER 10-5: PORTE REGISTER
R/W-0
R/W-0
U-0
U-0
RDPU
REPU
—
—
bit 7
The Data Latch register (LATE) is also memory
mapped. Read-modify-write operations on the LATE
register read and write the latched output value for
PORTE.
EXAMPLE 10-6: INITIALIZING PORTE
CLRF
MOVLB
BSF
BSF
MOVLW
MOVWF
LATE
0x0F
ANCON0,PCFG5
ANCON0,PCFG6
0x03
TRISE
;Initialize LATE output
;latch values
;ANCON registers not
;in access bank
;RE0/AN5 as digital
;RE1/AN6 as digital
;Example value used to
;initialize data direction
;RE0, RE1 as inputs
;RE2 as output
Each of the PORTE pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is per-
formed by setting bit, REPU (PORTE<6>). The weak
pull-up is automatically turned off when the port pin is
configured as an output. The pull-ups are disabled on a
POR. The integrated weak pull-ups consist of a semi-
conductor structure similar to, but somewhat different,
from a discrete resistor. On an unloaded I/O pin, the
weak pull-ups are intended to provide logic high indica-
tion, but will not necessarily pull the pin all the way to
VDD levels.
Note that the pull-ups can be used for any set of
features, similar to the pull-ups found on PORTB
U-0
R/W-0
R/W-0
R/W-0
—
RE2
RE1
RE0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
bit 6
bit 5-3
bit 2-0
RDPU: PORTD Pull-up Enable bit
1 = PORTD pull-ups are enabled by individual TRIS values
0 = All PORTD pull-ups are disabled
REPU: PORTE Pull-up Enable bit
1 = PORTE pull-ups are enabled by individual TRIS values
0 = All PORTE pull-ups are disabled
Unimplemented: Read as ‘0’
RE<2:0>: PORTE Data Input bits
DS39931D-page 148
 2011 Microchip Technology Inc.