PIC18F44J50-I Datasheet, PDF (286/562 Pages) Microchip Technology – 28/44-Pin, Low-Power, High-Performance USB Microcontrollers

PIC18F46J50 FAMILY
EXAMPLE 19-2:
512-BYTE SPI MASTER MODE Init AND TRANSFER
;For this example, let's use RP5(RB2) for SCK2,
;RP4(RB1) for SDO2, and RP3(RB0) for SDI2
;Let’s use SPI master mode, CKE = 0, CKP = 0,
;without using slave select signalling.
InitSPIPins:
movlb
0x0F
bcf
ODCON3, SPI2OD
;Select bank 15, for access to ODCON3 register
;Let’s not use open drain outputs in this example
bcf
LATB, RB2
bcf
LATB, RB1
bcf
TRISB, RB1
bcf
TRISB, RB2
bsf
TRISB, RB0
;Initialize our (to be) SCK2 pin low (idle).
;Initialize our (to be) SDO2 pin to an idle state
;Make SDO2 output, and drive low
;Make SCK2 output, and drive low (idle state)
;SDI2 is an input, make sure it is tri-stated
;Now we should unlock the PPS registers, so we can
;assign the MSSP2 functions to our desired I/O pins.
movlb
bcf
movlw
movwf
movlw
movwf
bcf
bsf
0x0E
INTCON, GIE
0x55
EECON2
0xAA
EECON2
PPSCON, IOLOCK
INTCON, GIE
;Select bank 14 for access to PPS registers
;I/O Pin unlock sequence will not work if CPU
;services an interrupt during the sequence
;Unlock sequence consists of writing 0x55
;and 0xAA to the EECON2 register.
;We may now write to RPINRx and RPORx registers
;May now turn back on interrupts if desired
movlw
movwf
0x03
RPINR21
;RP3 will be SDI2
;Assign the SDI2 function to pin RP3
movlw
movwf
movlw
movwf
movlw
movwf
movlb
0x0A
RPOR4
0x04
RPINR22
0x09
RPOR5
0x0F
;Let’s assign SCK2 output to pin RP4
;RPOR4 maps output signals to RP4 pin
;SCK2 also needs to be configured as an input on the
same pin
;SCK2 input function taken from RP4 pin
;0x09 is SDO2 output
;Assign SDO2 output signal to the RP5 (RB2) pin
;Done with PPS registers, bank 15 has other SFRs
InitMSSP2:
clrf
movlw
movwf
bsf
SSP2STAT
b'00000000'
SSP2CON1
SSP2CON1, SSPEN
;CKE = 0, SMP = 0 (sampled at middle of bit)
;CKP = 0, SPI Master mode, Fosc/4
;MSSP2 initialized
;Enable the MSSP2 module
InitSPIDMA:
movlw
movwf
movlw
movwf
b'00111010'
DMACON1
b'11110000'
DMACON2
;Full duplex, RX/TXINC enabled, no SSCON
;DLYINTEN is set, so DLYCYC3:DLYCYC0 = 1111
;Minimum delay between bytes, interrupt
;only once when the transaction is complete
DS39931D-page 286
 2011 Microchip Technology Inc.