PIC18F44J50-I Datasheet, PDF (94/562 Pages) Microchip Technology – 28/44-Pin, Low-Power, High-Performance USB Microcontrollers

PIC18F46J50 FAMILY
TABLE 6-4: REGISTER FILE SUMMARY (PIC18F46J50 FAMILY) (CONTINUED)
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on Details
POR, BOR on Page:
ANCON1
ANCON0
ODCON1
ODCON2
ODCON3
RTCCFG
RTCCAL
REFOCON
PADCFG1
UCFG
UADDR
UEIE
UIE
UEP15
UEP14
UEP13
UEP12
UEP11
UEP10
UEP9
UEP8
UEP7
UEP6
UEP5
UEP4
UEP3
UEP2
UEP1
UEP0
PPSCON
RPINR24
RPINR23
RPINR22
RPINR21
RPINR17
RPINR16
RPINR13
RPINR12
RPINR8
RPINR7
RPINR6
RPINR4
Legend:
Note 1:
2:
3:
4:
5:
6:
7:
VBGEN
r
—
PCFG12
PCFG11
PCFG10
PCFG9
PCFG8 00-0 0000 74, 348
PCFG7⁽⁵⁾ PCFG6⁽⁵⁾ PCFG5⁽⁵⁾ PCFG4
PCFG3
PCFG2
PCFG1
PCFG0 0000 0000 74, 347
—
—
—
—
—
—
ECCP20D ECCP10D ---- --00 74, 134
—
—
—
—
—
—
U2OD
U1OD ---- --00 74, 134
—
—
—
—
—
—
SPI2OD
SPI1OD ---- --00 74, 135
RTCEN
—
RTCWREN RTCSYNC HALFSEC
RTCOE
RTCPTR1 RTCPTR0 0-00 0000 74, 227
CAL7
CAL6
CAL5
CAL4
CAL3
CAL2
CAL1
CAL0 0000 0000 74, 228
ROON
—
ROSSLP ROSEL
RODIV3
RODIV2
RODIV1 RODIV0 0-00 0000 74, 44
—
—
—
—
—
RTSECSEL1 RTSECSEL0 PMPTTL ---- -000 74, 135
UTEYE UOEMON
—
UPUEN
UTRDIS
FSEN
PPB1
PPB0 00-0 0000 74, 360
—
ADDR6
ADDR5
ADDR4
ADDR3
ADDR2
ADDR1
ADDR0 -000 0000 74, 365
BTSEE
—
—
BTOEE
DFN8EE CRC16EE CRC5EE
PIDEE 0--0 0000 74, 377
—
SOFIE STALLIE IDLEIE
TRNIE
ACTVIE
UERRIE URSTIE -000 0000 74, 375
—
—
—
EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 74, 364
—
—
—
EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 74, 364
—
—
—
EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 74, 364
—
—
—
EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 74, 364
—
—
—
EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 74, 364
—
—
—
EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 74, 364
—
—
—
EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 74, 364
—
—
—
EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 74, 364
—
—
—
EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 74, 364
—
—
—
EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 75, 364
—
—
—
EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 75, 364
—
—
—
EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 75, 364
—
—
—
EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 75, 364
—
—
—
EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 75, 364
—
—
—
EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 75, 364
—
—
—
EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL ---0 0000 75, 364
—
—
—
—
—
—
—
IOLOCK ---- ---0 155
—
—
—
Input Function FLT0 to Input Pin Mapping Bits
---1 1111 75, 160
—
—
—
Input Function SS2 to Input Pin Mapping Bits
---1 1111 ^{75, 160}
—
—
—
Input Function SCK2 to Input Pin Mapping Bits
---1 1111 75, 160
—
—
—
Input Function SDI2 to Input Pin Mapping Bits
---1 1111 75, 159
—
—
—
Input Function CK2 to Input Pin Mapping Bits
---1 1111 75, 159
—
—
—
Input Function RX2DT2 to Input Pin Mapping Bits
---1 1111 75
—
—
—
Input Function T3G to Input Pin Mapping Bits
---1 1111 75
—
—
—
Input Function T1G to Input Pin Mapping Bits
---1 1111 75, 158
—
—
—
Input Function IC2 to Input Pin Mapping Bits
---1 1111 75, 158
—
—
—
Input Function IC1 to Input Pin Mapping Bits
---1 1111 75, 157
—
—
—
Input Function T3CKI to Input Pin Mapping Bits
---1 1111 75, 157
—
—
—
Input Function T0CKI to Input Pin Mapping Bits
---1 1111 75, 157
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved. Bold indicates shared access SFRs.
Bit 21 of the PC is only available in Serial Programming (SP) modes.
Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled.
The SSPxMSK registers are only accessible when SSPxCON2<3:0> = 1001.
Alternate names and definitions for these bits when the MSSP module is operating in I²C™ Slave mode. See Section 19.5.3.2 “Address
Masking Modes” for details.
These bits and/or registers are only available on 44-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset values are
shown for 44-pin devices.
The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the same physical registers and addresses, but have
different functions determined by the module’s operating mode. See Section 11.1.2 “Data Registers” for more information.
The TRISA6 and TRISA7 bits are only implemented when the pins are not configured for primary oscillator functions.
DS39931D-page 94
 2011 Microchip Technology Inc.