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PIC18F44J50-I Datasheet, PDF (292/562 Pages) Microchip Technology – 28/44-Pin, Low-Power, High-Performance USB Microcontrollers
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PIC18F46J50 FAMILY
REGISTER 19-8: SSPxCON2: MSSPx CONTROL REGISTER 2 (I2C™ SLAVE MODE)
(ACCESS FC5h, F71h)
R/W-0
GCEN
bit 7
R-0
ACKSTAT(2)
R/W-0
ADMSK5
R/W-0
ADMSK4
R/W-0
ADMSK3
R/W-0
ADMSK2
R/W-0
ADMSK1
R/W-0
SEN(1)
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
bit 6
bit 5-2
bit 1
bit 0
GCEN: General Call Enable bit (Slave mode only)
1 = Enables interrupt when a general call address (0000h) is received in the SSPxSR
0 = General call address is disabled
ACKSTAT: Acknowledge Status bit(2)
Unused in Slave mode.
ADMSK<5:2>: Slave Address Mask Select bits (5-Bit Address Masking)
1 = Masking of corresponding bits of SSPxADD is enabled
0 = Masking of corresponding bits of SSPxADD is disabled
ADMSK1: Slave Address Least Significant bit(s) Mask Select bit
In 7-Bit Addressing mode:
1 = Masking of SSPxADD<1> only is enabled
0 = Masking of SSPxADD<1> only is disabled
In 10-Bit Addressing mode:
1 = Masking of SSPxADD<1:0> is enabled
0 = Masking of SSPxADD<1:0> is disabled
SEN: Start Condition Enable/Stretch Enable bit(1)
1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)
0 = Clock stretching is disabled
Note 1:
2:
If the I2C module is active, these bits may not be set (no spooling) and the SSPxBUF may not be written
(or writes to the SSPxBUF are disabled).
This bit is unimplemented in I2C Slave mode.
REGISTER 19-9: SSPxMSK: I2C™ SLAVE ADDRESS MASK REGISTER (7-BIT MASKING MODE)
(ACCESS FC8h, F74h)(1)
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
MSK7
MSK6
MSK5
MSK4
MSK3
MSK2
MSK1
MSK0(2)
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-0
MSK<7:0>: Slave Address Mask Select bits
1 = Masking of corresponding bit of SSPxADD is enabled
0 = Masking of corresponding bit of SSPxADD is disabled
Note 1: This register shares the same SFR address as SSPxADD and is only addressable in select MSSP
operating modes. See Section 19.5.3.4 “7-Bit Address Masking Mode” for more details.
2: MSK0 is not used as a mask bit in 7-bit addressing.
DS39931D-page 292
 2011 Microchip Technology Inc.
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