PIC18F44J50-I Datasheet, PDF (193/562 Pages) Microchip Technology – 28/44-Pin, Low-Power, High-Performance USB Microcontrollers

PIC18F46J50 FAMILY
TABLE 11-2: REGISTERS ASSOCIATED WITH PMP MODULE
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on Page:
INTCON
GIE/GIEH PEIE/GIEL TMR0IE INT0IE
RBIE
TMR0IF
INT0IF
RBIF
69
PIR1
PMPIF⁽²⁾ ADIF RC1IF TX1IF
SSP1IF CCP1IF
TMR2IF TMR1IF 72
PIE1
PMPIE⁽²⁾ ADIE RC1IE TX1IE SSP1IE CCP1IE
TMR2IE TMR1IE 72
IPR1
PMPIP⁽²⁾ ADIP RC1IP TX1IP SSP1IP CCP1IP
TMR2IP TMR1IP 72
PMCONH⁽²⁾
PMPEN
—
— ADRMUX1 ADRMUX0 PTBEEN PTWREN PTRDEN 74
PMCONL⁽²⁾
CSF1
CSF0
ALP
—
CS1P
BEP
WRSP
RDSP
74
PMADDRH^(1,2)/
—
CS1 Parallel Master Port Address High Byte
73
PMDOUT1H^(1,2) Parallel Port Out Data High Byte (Buffer 1)
73
PMADDRL^(1,2)/ Parallel Master Port Address Low Byte
73
PMDOUT1L^(1,2) Parallel Port Out Data Low Byte (Buffer 0)
73
PMDOUT2H⁽²⁾ Parallel Port Out Data High Byte (Buffer 3)
74
PMDOUT2L⁽²⁾ Parallel Port Out Data Low Byte (Buffer 2)
74
PMDIN1H⁽²⁾ Parallel Port In Data High Byte (Buffer 1)
73
PMDIN1L⁽²⁾
Parallel Port In Data Low Byte (Buffer 0)
73
PMDIN2H⁽²⁾ Parallel Port In Data High Byte (Buffer 3)
74
PMDIN2L⁽²⁾
Parallel Port In Data Low Byte (Buffer 2)
74
PMMODEH⁽²⁾
BUSY IRQM1 IRQM0 INCM1 INCM0 MODE16 MODE1 MODE0 74
PMMODEL⁽²⁾
WAITB1 WAITB0 WAITM3 WAITM2 WAITM1 WAITM0
WAITE1 WAITE0
74
PMEH⁽²⁾
—
PTEN14
—
—
—
—
—
—
74
PMEL⁽²⁾
PTEN7 PTEN6 PTEN5 PTEN4 PTEN3
PTEN2
PTEN1 PTEN0
74
PMSTATH⁽²⁾
IBF
IBOV
—
—
IB3F
IB2F
IB1F
IB0F
74
PMSTATL⁽²⁾
OBE
OBUF
—
—
OB3E
OB2E
OB1E
OB0E
74
PADCFG1
—
—
—
—
—
RTSECSEL1 RTSECSEL0 PMPTTL 74
Legend:
Note 1:
2:
— = unimplemented, read as ‘0’. Shaded cells are not used during PMP operation.
The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the physical registers and
addresses, but have different functions, determined by the module’s operating mode.
These bits and/or registers are only available on 44-pin devices.
 2011 Microchip Technology Inc.
DS39931D-page 193