PIC18F44J50-I Datasheet, PDF (138/562 Pages) Microchip Technology – 28/44-Pin, Low-Power, High-Performance USB Microcontrollers

PIC18F46J50 FAMILY
TABLE 10-3: PORTA I/O SUMMARY (CONTINUED)
Pin
Function
TRIS
Setting
I/O
I/O
Type
Description
RA5/AN4/SS1/
RA5
HLVDIN/RCV/
RP2
0
O DIG LATA<5> data output; not affected by analog input.
1
I TTL PORTA<5> data input; disabled when analog input is
enabled.
AN4
1
I ANA A/D Input Channel 4. Default configuration on POR.
SS1
1
I TTL Slave select input for MSSP1.
HLVDIN
1
I ANA High/Low-Voltage Detect external trip point reference input.
RCV
1
I TTL External USB transceiver RCV input.
RP2
1
I ST Remappable Peripheral Pin 2 input.
0
O DIG Remappable Peripheral Pin 2 output.
OSC2/CLKO/
OSC2
x
O ANA Main oscillator feedback output connection (HS mode).
RA6
CLKO
x
O DIG System cycle clock output (FOSC/4) in RC and EC Oscillator
modes.
RA6
1
I TTL PORTA<6> data input.
0
O DIG LATA<6> data output.
OSC1/CLKI/RA7 OSC1
1
I ANA Main oscillator input connection.
CLKI
1
I ANA Main clock input connection.
RA7
1
I TTL PORTA<6> data input.
0
O DIG LATA<6> data output.
Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level
input/output; x = Don’t care (TRIS bit does not affect port direction or is overridden for this option)
Note 1: This bit is only available on 44-pin devices.
TABLE 10-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PORTA
RA7
RA6
RA5
—
RA3
RA2
RA1
RA0
LATA
LAT7
LAT6
LAT5
—
LAT3
LAT2
LAT1
LAT0
TRISA
TRIS7 TRIS6 TRISA5
—
TRISA3 TRISA2 TRISA1 TRISA0
ANCON0
PCFG7⁽¹⁾ PCFG6⁽¹⁾ PCFG5⁽¹⁾ PCFG4 PCFG3 PCFG2 PCFG1 PCFG0
CMxCON
CON
COE
CPOL EVPOL1 EVPOL0 CREF CCH1 CCH0
CVRCON
CVREN CVROE CVRR
r
CVR3 CVR2 CVR1 CVR0
Legend: — = unimplemented, read as ‘0’, r = reserved. Shaded cells are not used by PORTA.
Note 1: These bits are only available on 44-pin devices.
Reset
Values
on Page
87
92
92
90
90
93
DS39931D-page 138
 2011 Microchip Technology Inc.