PIC18F44J50-I Datasheet, PDF (432/562 Pages) Microchip Technology – 28/44-Pin, Low-Power, High-Performance USB Microcontrollers

PIC18F46J50 FAMILY
FIGURE 27-4:
Peripheral
Clock
FSCM BLOCK DIAGRAM
Clock Monitor
Latch
(edge-triggered)
SQ
INTRC
Source
(32 s)
÷ 64
488 Hz
(2.048 ms)
C
Q
Clock
Failure
Detected
Clock failure is tested for on the falling edge of the
sample clock. If a sample clock falling edge occurs
while the clock monitor is still set, and a clock failure
has been detected (Figure 27-5), the following results:
• The FSCM generates an oscillator fail interrupt by
setting bit, OSCFIF (PIR2<7>).
• The device clock source is switched to the internal
oscillator block (OSCCON is not updated to show
the current clock source – this is the Fail-safe
condition).
• The WDT is reset.
During switchover, the postscaler frequency from the
internal oscillator block may not be sufficiently stable
for timing-sensitive applications. In these cases, it may
FIGURE 27-5:
FSCM TIMING DIAGRAM
Sample Clock
Device
Clock
Output
Clock Monitor
Output (Q)
OSCFIF
be desirable to select another clock configuration and
enter an alternate power-managed mode. This can be
done to attempt a partial recovery or execute a
controlled shutdown. See Section 4.1.4 “Multiple
Sleep Commands” and Section 27.4.1 “Special
Considerations for Using Two-Speed Start-up” for
more details.
The FSCM will detect failures of the primary or secondary
clock sources only. If the internal oscillator block fails, no
failure would be detected, nor would any action be
possible.
27.5.1 FSCM AND THE WATCHDOG TIMER
Both the FSCM and the WDT are clocked by the
INTRC oscillator. Since the WDT operates with a
separate divider and counter, disabling the WDT has
no effect on the operation of the INTRC oscillator when
the FSCM is enabled.
As already noted, the clock source is switched to the
INTRC clock when a clock failure is detected; this may
mean a substantial change in the speed of code execu-
tion. If the WDT is enabled with a small prescale value,
a decrease in clock speed allows a WDT time-out to
occur and a subsequent device Reset. For this reason,
Fail-Safe Clock Monitor events also reset the WDT and
postscaler, allowing it to start timing from when execu-
tion speed was changed and decreasing the likelihood
of an erroneous time-out.
Oscillator
Failure
Failure
Detected
Note:
Clock Monitor Test
Clock Monitor Test
Clock Monitor Test
The device clock is normally at a much higher frequency than the sample clock. The relative frequencies in
this example have been chosen for clarity.
DS39931D-page 432
 2011 Microchip Technology Inc.