PIC18F44J50-I Datasheet, PDF (448/562 Pages) Microchip Technology – 28/44-Pin, Low-Power, High-Performance USB Microcontrollers

PIC18F46J50 FAMILY
BTFSC
Bit Test File, Skip if Clear
Syntax:
BTFSC f, b {,a}
Operands:
0  f  255
0b7
a [0,1]
Operation:
skip if (f<b>) = 0
Status Affected:
None
Encoding:
1011 bbba ffff ffff
Description:
If bit ‘b’ in register, ‘f’, is ‘0’, then the
next instruction is skipped. If bit, ‘b’, is
‘0’, then the next instruction fetched
during the current instruction execu-
tion is discarded and a NOP is executed
instead, making this a two-cycle
instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
Words:
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 28.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
1
Cycles:
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q2
Q3
Decode
Read
register ‘f’
Process
Data
If skip:
Q1
Q2
Q3
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Q4
No
operation
Q4
No
operation
Q4
No
operation
No
operation
Example:
HERE
FALSE
TRUE
BTFSC
:
:
FLAG, 1, 0
Before Instruction
PC
=
After Instruction
If FLAG<1> =
PC
=
If FLAG<1> =
PC
=
address (HERE)
0;
address (TRUE)
1;
address (FALSE)
BTFSS
Bit Test File, Skip if Set
Syntax:
BTFSS f, b {,a}
Operands:
0  f  255
0b<7
a [0,1]
Operation:
skip if (f<b>) = 1
Status Affected:
None
Encoding:
1010 bbba ffff ffff
Description:
If bit ‘b’ in register, ‘f’, is ‘1’, then the
next instruction is skipped. If bit, ‘b’, is
‘1’, then the next instruction fetched
during the current instruction execu-
tion is discarded and a NOP is executed
instead, making this a two-cycle
instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
Words:
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 28.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
1
Cycles:
1(2)
Note:
3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q2
Q3
Decode
Read
register ‘f’
Process
Data
If skip:
Q1
Q2
Q3
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Q4
No
operation
Q4
No
operation
Q4
No
operation
No
operation
Example:
HERE
FALSE
TRUE
BTFSS
:
:
FLAG, 1, 0
Before Instruction
PC
=
After Instruction
If FLAG<1> =
PC
=
If FLAG<1> =
PC
=
address (HERE)
0;
address (FALSE)
1;
address (TRUE)
DS39931D-page 448
 2011 Microchip Technology Inc.