PIC18F44J50-I Datasheet, PDF (557/562 Pages) Microchip Technology – 28/44-Pin, Low-Power, High-Performance USB Microcontrollers

PIC18F46J50 FAMILY
I²C Slave Mode (7-Bit Reception, SEN = 0,
ADMSK = 01011) ............................................. 298
I²C Slave Mode (7-Bit Reception, SEN = 0) ............ 297
I²C Slave Mode (7-Bit Reception, SEN = 1) ............ 305
I²C Slave Mode (7-Bit Transmission) ....................... 299
I²C Slave Mode General Call Address
Sequence (7 or 10-Bit Addressing Mode) ........ 307
I²C Stop Condition Receive or Transmit Mode ........ 316
Low-Voltage Detect (VDIRMAG = 0) ....................... 398
MSSPx I²C Bus Data ............................................... 526
MSSPx I²C Bus Start/Stop Bits ................................ 526
Parallel Master Port Read ........................................ 517
Parallel Master Port Write ........................................ 518
Parallel Slave Port ................................................... 519
Parallel Slave Port Read .................................. 179, 181
Parallel Slave Port Write .................................. 179, 182
PWM Auto-Shutdown with Auto-Restart Enabled .... 262
PWM Auto-Shutdown with Firmware Restart ........... 262
PWM Direction Change ........................................... 259
PWM Direction Change at Near 100% Duty Cycle .. 260
PWM Output ............................................................ 250
PWM Output (Active-High) ....................................... 254
PWM Output (Active-Low) ....................................... 255
Read and Write, 8-Bit Data, Demultiplexed
Address ............................................................ 186
Read, 16-Bit Data, Demultiplexed Address ............. 189
Read, 16-Bit Multiplexed Data, Fully
Multiplexed 16-Bit Address .............................. 190
Read, 16-Bit Multiplexed Data, Partially
Multiplexed Address ........................................ 189
Read, 8-Bit Data, Fully Multiplexed
16-Bit Address ................................................. 188
Read, 8-Bit Data, Partially Multiplexed Address ...... 186
Read, 8-Bit Data, Partially Multiplexed
Address, Enable Strobe ................................... 187
Read, 8-Bit Data, Wait States Enabled,
Partially Multiplexed Address ........................... 186
Repeated Start Condition ......................................... 312
Reset, Watchdog Timer (WDT), Oscillator Start-up
Timer (OST) and Power-up Timer (PWRT) ..... 513
Send Break Character Sequence ............................ 340
Slave Synchronization ............................................. 276
Slow Rise Time (MCLR Tied to VDD,
VDD Rise > TPWRT) ............................................ 67
SPI Mode (Master Mode) ......................................... 275
SPI Mode (Slave Mode, CKE = 0) ........................... 277
SPI Mode (Slave Mode, CKE = 1) ........................... 277
Steering Event at Beginning of Instruction
(STRSYNC = 1) ............................................... 266
Steering Event at End of Instruction
(STRSYNC = 0) ............................................... 266
Synchronous Reception (Master Mode, SREN) ...... 343
Synchronous Transmission ...................................... 341
Synchronous Transmission (Through TXEN) .......... 342
Time-out Sequence on Power-up
(MCLR Not Tied to VDD), Case 1 ....................... 67
Time-out Sequence on Power-up
(MCLR Not Tied to VDD), Case 2 ....................... 67
Time-out Sequence on Power-up
(MCLR Tied to VDD, VDD Rise < TPWRT) ........... 66
Timer Pulse Generation ........................................... 242
Timer0 and Timer1 External Clock .......................... 515
Timer1 Gate Count Enable Mode ............................ 207
Timer1 Gate Single Pulse Mode .............................. 209
Timer1 Gate Single Pulse/Toggle
Combined Mode .............................................. 210
Timer1 Gate Toggle Mode ....................................... 208
Timer3 Gate Count Enable Mode ............................ 217
Timer3 Gate Single Pulse Mode .............................. 219
Timer3 Gate Single Pulse/Toggle
Combined Mode .............................................. 220
Timer3 Gate Toggle Mode ....................................... 218
Transition for Entry to Idle Mode ............................... 52
Transition for Entry to SEC_RUN Mode .................... 49
Transition for Entry to Sleep Mode ............................ 51
Transition for Two-Speed Start-up
(INTRC to HSPLL) ........................................... 431
Transition for Wake From Idle to Run Mode .............. 53
Transition for Wake From Sleep (HSPLL) ................. 51
Transition From RC_RUN Mode to
PRI_RUN Mode ................................................. 50
Transition From SEC_RUN Mode to
PRI_RUN Mode (HSPLL) .................................. 49
Transition to RC_RUN Mode ..................................... 50
USB Signal .............................................................. 530
Write, 16-Bit Data, Demultiplexed Address ............. 189
Write, 16-Bit Multiplexed Data, Fully
Multiplexed 16-Bit Address .............................. 190
Write, 16-Bit Multiplexed Data, Partially
Multiplexed Address ........................................ 190
Write, 8-Bit Data, Fully Multiplexed
16-Bit Address ................................................. 188
Write, 8-Bit Data, Partially Multiplexed Address ...... 187
Write, 8-Bit Data, Partially Multiplexed
Address, Enable Strobe ................................... 188
Write, 8-Bit Data, Wait States Enabled,
Partially Multiplexed Address .......................... 187
Timing Diagrams and Specifications
AC Characteristics
Internal RC Accuracy ....................................... 511
CLKO and I/O Requirements ................................... 512
Enhanced Capture/Compare/PWM
Requirements .................................................. 516
EUSARTx Synchronous Receive Requirements ..... 528
EUSARTx Synchronous Transmission
Requirements .................................................. 528
Example SPI Mode Requirements
(Master Mode, CKE = 0) .................................. 520
Example SPI Mode Requirements
(Master Mode, CKE = 1) .................................. 521
Example SPI Mode Requirements
(Slave Mode, CKE = 0) .................................... 522
Example SPI Slave Mode Requirements
(CKE = 1) ......................................................... 523
External Clock Requirements .................................. 510
I²C Bus Data Requirements (Slave Mode) .............. 525
I²C Bus Start/Stop Bits Requirements
(Slave Mode) ................................................... 524
Low-Power Wake-up Time ...................................... 514
MSSPx I²C Bus Data Requirements ....................... 527
MSSPx I²C Bus Start/Stop Bits Requirements ........ 526
Parallel Master Port Read Requirements ................ 517
Parallel Master Port Write Requirements ................ 518
Parallel Slave Port Requirements ............................ 519
PLL Clock ................................................................ 511
Reset, Watchdog Timer, Oscillator Start-up
Timer, Power-up Timer and Brown-out
Reset Requirements ........................................ 513
Timer0 and Timer1 External Clock Requirements ... 515
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