PIC18F44J50-I Datasheet, PDF (87/562 Pages) Microchip Technology – 28/44-Pin, Low-Power, High-Performance USB Microcontrollers

PIC18F46J50 FAMILY
6.3.5 SPECIAL FUNCTION REGISTERS
The SFRs are registers used by the CPU and periph-
eral modules for controlling the desired operation of the
device. These registers are implemented as static
RAM. SFRs start at the top of data memory (FFFh) and
extend downward to occupy more than the top half of
Bank 15 (F40h to FFFh). Table 6-2, Table 6-3 and
Table 6-4 provide a list of these registers.
The SFRs can be classified into two sets: those
associated with the “core” device functionality (ALU,
Resets and interrupts) and those related to the
peripheral functions. The Reset and Interrupt registers
are described in their corresponding chapters, while the
ALU’s STATUS register is described later in this section.
Registers related to the operation of the peripheral
features are described in the chapter for that peripheral.
The SFRs are typically distributed among the
peripherals whose functions they control. Unused SFR
locations are unimplemented and read as ‘0’s
Note:
The SFRs, located between EC0h and F5Fh,
are not part of the Access Bank. Either
BANKED instructions (using BSR) or the
MOVFF instruction should be used to access
these locations. When programming in
MPLAB^® C18, the compiler will automatically
use the appropriate addressing mode.
TABLE 6-2: ACCESS BANK SPECIAL FUNCTION REGISTER MAP
Address
Name
Address
Name
Address Name Address Name Address
Name
FFFh
FFEh
FFDh
FFCh
FFBh
FFAh
FF9h
FF8h
FF7h
FF6h
FF5h
FF4h
FF3h
FF2h
FF1h
FF0h
FEFh
FEEh
FEDh
FECh
FEBh
FEAh
FE9h
FE8h
FE7h
FE6h
FE5h
FE4h
FE3h
FE2h
FE1h
FE0h
TOSU
TOSH
TOSL
STKPTR
PCLATU
PCLATH
PCL
TBLPTRU
TBLPTRH
TBLPTRL
TABLAT
PRODH
PRODL
INTCON
INTCON2
INTCON3
INDF0⁽¹⁾
POSTINC0⁽¹⁾
POSTDEC0⁽¹⁾
PREINC0⁽¹⁾
PLUSW0⁽¹⁾
FSR0H
FSR0L
WREG
INDF1⁽¹⁾
POSTINC1⁽¹⁾
POSTDEC1⁽¹⁾
PREINC1⁽¹⁾
PLUSW1⁽¹⁾
FSR1H
FSR1L
BSR
FDFh
FDEh
FDDh
FDCh
FDBh
FDAh
FD9h
FD8h
FD7h
FD6h
FD5h
FD4h
FD3h
FD2h
FD1h
FD0h
FCFh
FCEh
FCDh
FCCh
FCBh
FCAh
FC9h
FC8h
FC7h
FC6h
FC5h
FC4h
FC3h
FC2h
FC1h
FC0h
INDF2⁽¹⁾
POSTINC2⁽¹⁾
POSTDEC2⁽¹⁾
PREINC2⁽¹⁾
PLUSW2⁽¹⁾
FSR2H
FSR2L
STATUS
TMR0H
TMR0L
T0CON
—⁽⁵⁾
OSCCON
CM1CON
CM2CON
RCON
TMR1H
TMR1L
T1CON
TMR2
PR2
T2CON
SSP1BUF
SSP1ADD⁽³⁾
SSP1STAT
SSP1CON1
SSP1CON2
ADRESH
ADRESL
ADCON0
ADCON1
WDTCON
FBFh
FBEh
FBDh
FBCh
FBBh
FBAh
FB9h
FB8h
FB7h
FB6h
FB5h
FB4h
FB3h
FB2h
FB1h
FB0h
FAFh
FAEh
FADh
FACh
FABh
FAAh
FA9h
FA8h
FA7h
FA6h
FA5h
FA4h
FA3h
FA2h
FA1h
FA0h
PSTR1CON
ECCP1AS
ECCP1DEL
CCPR1H
CCPR1L
CCP1CON
PSTR2CON
ECCP2AS
ECCP2DEL
CCPR2H
CCPR2L
CCP2CON
CTMUCONH
CTMUCONL
CTMUICON
SPBRG1
RCREG1
TXREG1
TXSTA1
RCSTA1
SPBRG2
RCREG2
TXREG2
TXSTA2
EECON2
EECON1
IPR3
PIR3
PIE3
IPR2
PIR2
PIE2
F9Fh
F9Eh
F9Dh
F9Ch
F9Bh
F9Ah
F99h
F98h
F97h
F96h
F95h
F94h
F93h
F92h
F91h
F90h
F8Fh
F8Eh
F8Dh
F8Ch
F8Bh
F8Ah
F89h
F88h
F87h
F86h
F85h
F84h
F83h
F82h
F81h
F80h
IPR1
PIR1
PIE1
RCSTA2
OSCTUNE
T1GCON
RTCVALH
RTCVALL
T3GCON
TRISE
TRISD
TRISC
TRISB
TRISA
ALRMCFG
ALRMRPT
ALRMVALH
ALRMVALL
LATE⁽²⁾
LATD⁽²⁾
LATC
LATB
LATA
DMACON1
—⁽⁵⁾
DMACON2
HLVDCON
PORTE⁽²⁾
PORTD⁽²⁾
PORTC
PORTB
PORTA
F7Fh
F7Eh
F7Dh
F7Ch
F7Bh
F7Ah
F79h
F78h
F77h
F76h
F75h
F74h
F73h
F72h
F71h
F70h
F6Fh
F6Eh
F6Dh
F6Ch
F6Bh
F6Ah
F69h
F68h
F67h
F66h
F65h
F64h
F63h
F62h
F61h
F60h
SPBRGH1
BAUDCON1
SPBRGH2
BAUDCON2
TMR3H
TMR3L
T3CON
TMR4
PR4
T4CON
SSP2BUF
SSP2ADD⁽³⁾
SSP2STAT
SSP2CON1
SSP2CON2
CMSTAT
PMADDRH^(2,4)
PMADDRL^(2,4)
PMDIN1H⁽²⁾
PMDIN1L⁽²⁾
TXADDRL
TXADDRH
RXADDRL
RXADDRH
DMABCL
DMABCH
UCON
USTAT
UEIR
UIR
UFRMH
UFRML
Note 1:
2:
3:
4:
5:
This is not a physical register.
This register is not available on 28-pin devices.
SSPxADD and SSPxMSK share the same address.
PMADDRH and PMDOUTH share the same address, and PMADDRL and PMDOUTL share the same address.
PMADDRx is used in Master modes and PMDOUTx is used in Slave modes.
Reserved; do not write to this location.
 2011 Microchip Technology Inc.
DS39931D-page 87